X9000 Datasheet, PDF (34/77 Pages) Intel Corporation – Core2 Duo Processor and Core2 Extreme Processor on 45-nm Process

Electrical Specifications
Figure 6.
Deeper Sleep V_CC and I_CC Loadline Standard Voltage and Extreme Edition
Processors
V_CC-CORE [V]
VCC-CORE max {HFM|LFM}
VCC-CORE, DC max {HFM|LFM}
VCC-CORE nom {HFM|LFM}
Slope = -2.1 mV/A at package
VccSense, VssSense pins.
Differential Remote Sense required.
13mV= RIPPLE
Table 8.
VCC-CORE, DC min {HFM|LFM}
VCC-CORE min {HFM|LFM}
+/-VCC-CORE Tolerance
= VR St. Pt. Error 1/
0
ICC-CORE max
{HFM|LFM}
Note 1/ VCC-CORE Set Point Error Tolerance is per below:
I_CC-CORE
[A]
Tolerance VCC-CORE VID Voltage Range
--------------- --------------------------------------------------------
+/-[(VID*1.5%)-3mV]
VCC-CORE > 0.7500V
+/-(11.5mV-3mV)
0.5000V </= VCC-CORE </= 0.7500V
Total tolerance window
including ripple is +/-35mV for C6
0.3000V </= VCC-CORE < 0.5000V
NOTE: Deeper Sleep mode tolerance depends on VID value.
FSB Differential BCLK Specifications
Symbol
Parameter
Min
V_CROSS
ΔV_CROSS
V_SWING
I_LI
Cpad
Crossing Voltage
Range of Crossing Points
Differential Output Swing
Input Leakage Current
Pad Capacitance
0.3
—
300
-5
0.95
Typ
—
—
—
—
1.2
Max
0.55
140
—
+5
1.45
Unit
V
mV
mV
µA
pF
Notes¹
2, 7, 8
2, 7, 5
6
3
4
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the
falling edge of BCLK1.
3.
For V_in between 0 V and V_IH.
4.
Cpad includes die capacitance only. No package parasitics are included.
5.
ΔV_CROSS is defined as the total variation of all crossing voltages as defined in note 2.
6.
Measurement taken from differential waveform.
7.
Measurement taken from single-ended waveform.
8.
Only applies to the differential rising edge (Clock rising and Clock# falling).
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Datasheet