X9000 Datasheet, PDF (35/77 Pages) Intel Corporation – Core2 Duo Processor and Core2 Extreme Processor on 45-nm Process

Electrical Specifications
Table 9.
AGTL+ Signal Group DC Specifications
Symbol
Parameter
Min
V_CCP
GTLREF
I/O Voltage
Reference Voltage
R_COMP
R_ODT/A
R_ODT/D
R_ODT/Cntrl
V_IH
V_IL
V_OH
R_TT/A
R_TT/D
R_TT/Cntrl
R_ON/A
R_ON/D
R_ON/Cntrl
I_LI
Cpad
Compensation Resistor
Termination Resistor Address
Termination Resistor Data
Termination Resistor Control
Input High Voltage
Input Low Voltage
Output High Voltage
Termination Resistance Address
Termination Resistance Data
Termination Resistance Control
Buffer On Resistance Address
Buffer On Resistance Data
Buffer On Resistance Control
Input Leakage Current
Pad Capacitance
1.00
0.65
27.23
48
48
48
0.82
-0.10
0.90
48
48
48
22
22
22
—
1.80
Typ
1.05
0.70
27.5
55
55
55
1.05
0
V_CCP
55
55
55
25
25
25
—
2.30
Max
1.10
0.72
27.78
65
64
65
1.20
0.55
1.10
65
64
65
30
29.5
30
±100
2.75
Unit Notes¹
V
V
6
Ω
10
Ω 11, 12
Ω 11, 13
Ω 11, 14
V
3, 6
V
2, 4
V
6
Ω
7, 12
Ω
7, 13
Ω
7, 14
Ω
5, 12
Ω
5, 13
Ω
5, 14
µA
8
pF
9
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
V_IL is defined as the maximum voltage level at a receiving agent that will be interpreted as
a logical low value.
3.
V_IH is defined as the minimum voltage level at a receiving agent that will be interpreted as
a logical high value.
4.
V_IH and V_OH may experience excursions above V_CCP. However, input signal drivers must
comply with the signal quality specifications.
5.
This is the pull-down driver resistance. Refer to processor I/O Buffer Models for I/V
characteristics. Measured at 0.31*V_CCP. R_ON (min) = 0.4*R_TT, R_ON (typ) = 0.455*R_TT,
R_ON (max) = 0.51*R_TT. R_TT typical value of 55 Ω is used for R_ON typ/min/max calculations.
6.
GTLREF should be generated from V_CCP with a 1% tolerance resistor divider. The V_CCP
referred to in these specifications is the instantaneous V_CCP.
7.
R_TT is the on-die termination resistance measured at V_OL of the AGTL+ output driver.
Measured at 0.31*V_CCP. R_TT is connected to V_CCP on die. Refer to processor I/O buffer
models for I/V characteristics.
8.
Specified with on die R_TT and R_ON are turned off. V_in between 0 and V_CCP.
9.
Cpad includes die capacitance only. No package parasitics are included.
10. This is the external resistor on the comp pins.
11. On-die termination resistance, measured at 0.33*V_CCP.
12. Applies to Signals A[35:3].
13. Applies to Signals D[63:0].
14. Applies to Signals BPRI#,DEFER#,PREQ#, RESET#, RS[2:0]#, TRDY#, ADS#, BNR#,
BPM[3:0], BR0#, DBSY#, DRDY#, DRDY#, HIT#, HITM#, LOCK#, PRDY#, DPWR#,
ADSTB[1:0]#, DSTBP[3:0] and DSTBN[3:0]#.
Datasheet
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