X9000 Datasheet, PDF (15/77 Pages) Intel Corporation – Core2 Duo Processor and Core2 Extreme Processor on 45-nm Process

Low Power Features
2.1.1.7
2.1.2
2.1.2.1
2.1.2.2
Core C6 State
C6 is a radical, new, power-saving state which is being implemented on this processor.
In C6 the processor saves its entire architectural state onto an on-die SRAM, hence
allowing it to run at a voltage V_C6 that is lower than Enhanced Deeper Sleep voltage.
An individual core of the dual-core processor can enter the C6 state by initiating a
P_LVL6 I/O read to the P_BLK or an MWAIT(C6) instruction. The primary method to
enter C6 used by newer operating systems (that support MWAIT) will be through the
MWAIT instruction.
When the core enters C6, it saves the processor state that is relevant to the processor
context in an on-die SRAM that resides on a separate power plane V_CCP (I/O power
supply). This allows the main core V_CC to be lowered to a very low-voltage V_C6. The on-
die storage for saving the processor state is implemented as a per-core SRAM. The
microcode performs the save and restore of the processor state on entry and exit from
C6, respectively.
Package Low-Power State Descriptions
Normal State
This is the normal operating state for the processor. The processor remains in the
Normal state when at least one of its cores is in the C0, C1/AutoHALT, or C1/MWAIT
state.
Stop-Grant State
When the STPCLK# pin is asserted, each core of the dual-core processor enters the
Stop-Grant state within 20 bus clocks after the response phase of the processor-issued
Stop-Grant Acknowledge special bus cycle. Processor cores that are already in the C2,
C3, or C4 state remain in their current low-power state. When the STPCLK# pin is
deasserted, each core returns to its previous core low-power state.
Since the AGTL+ signal pins receive power from the FSB, these pins should not be
driven (allowing the level to return to V_CCP) for minimum power drawn by the
termination resistors in this state. In addition, all other input pins on the FSB should be
driven to the inactive state.
RESET# causes the processor to immediately initialize itself, but the processor will stay
in Stop-Grant state. When RESET# is asserted by the system, the STPCLK#, SLP#,
DPSLP#, and DPRSTP# pins must be deasserted prior to RESET# deassertion as per AC
Specification T45. When re-entering the Stop-Grant state from the Sleep state,
STPCLK# should be deasserted after the deassertion of SLP#, as per AC Specification
T75.
While in Stop-Grant state, the processor will service snoops and latch interrupts
delivered on the FSB. The processor will latch SMI#, INIT# and LINT[1:0] interrupts
and will service only one of each upon return to the Normal state.
The PBE# signal may be driven when the processor is in the Stop-Grant state. PBE#
will be asserted if there is any pending interrupt or Monitor event latched within the
processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still
cause assertion of PBE#. Assertion of PBE# indicates to system logic that the entire
processor should return to the Normal state.
A transition to the Stop-Grant Snoop state occurs when the processor detects a snoop
on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see Section 2.1.2.4)
occurs with the assertion of the SLP# signal.
Datasheet
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