X9000 Datasheet, PDF (64/77 Pages) Intel Corporation – Core2 Duo Processor and Core2 Extreme Processor on 45-nm Process

Package Mechanical Specifications and Pin Information
Table 14.
Signal Description (Sheet 3 of 8)
Name
Type
Description
DBSY#
DEFER#
DINV[3:0]#
Input/
Output
Input
Input/
Output
DBSY# (Data Bus Busy) is asserted by the agent responsible for
driving data on the FSB to indicate that the data bus is in use. The
data bus is released after DBSY# is deasserted. This signal must
connect the appropriate pins on both FSB agents.
DEFER# is asserted by an agent to indicate that a transaction
cannot be ensured in-order completion. Assertion of DEFER# is
normally the responsibility of the addressed memory or input/
output agent. This signal must connect the appropriate pins of both
FSB agents.
DINV[3:0]# (Data Bus Inversion) are source synchronous and
indicate the polarity of the D[63:0]# signals. The DINV[3:0]#
signals are activated when the data on the data bus is inverted. The
bus agent will invert the data bus signals if more than half the bits,
within the covered group, would change level in the next cycle.
DINV[3:0]# Assignment to Data Bus
Bus Signal
Data Bus Signals
DINV[3]#
DINV[2]#
DINV[1]#
DINV[0]#
D[63:48]#
D[47:32]#
D[31:16]#
D[15:0]#
DPRSTP#
DPSLP#
DPWR#
DRDY#
Input
Input
Input/
Output
Input/
Output
DPRSTP#, when asserted on the platform, causes the processor to
transition from the Deep Sleep State to the Deeper Sleep state or
C6 state. To return to the Deep Sleep State, DPRSTP# must be
deasserted. DPRSTP# is driven by the ICH8M chipset.
DPSLP# when asserted on the platform causes the processor to
transition from the Sleep State to the Deep Sleep state. To return to
the Sleep State, DPSLP# must be deasserted. DPSLP# is driven by
the ICH8M chipset.
DPWR# is a control signal used by the chipset to reduce power on
the processor data bus input buffers. The processor drives this pin
during dynamic FSB frequency switching.
DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-common
clock data transfer, DRDY# may be deasserted to insert idle clocks.
This signal must connect the appropriate pins of both FSB agents.
Data strobe used to latch in D[63:0]#.
DSTBN[3:0]#
Input/
Output
Signals
D[15:0]#, DINV[0]#
D[31:16]#, DINV[1]#
D[47:32]#, DINV[2]#
D[63:48]#, DINV[3]#
Associated Strobe
DSTBN[0]#
DSTBN[1]#
DSTBN[2]#
DSTBN[3]#
64
Datasheet