X9000 Datasheet, PDF (13/77 Pages) Intel Corporation – Core2 Duo Processor and Core2 Extreme Processor on 45-nm Process

Low Power Features
Figure 2. Package Low-Power States
Normal
STPCLK# asserted
STPCLK# de-asserted
Stop
Grant
SLP# asserted
SLP# de-asserted
Sleep
DPSLP# asserted
Deep
Sleep
DPSLP# de-asserted
DPRSTP# asserted
Deeper
Sleep^†
DPRSTP# de-asserted
Snoop Snoop
serviced occurs
Stop
Grant
Snoop
† — Deeper Sleep includes the Deeper Sleep state, Intel Enhanced Deeper Sleep state, and C6 state
Table 1.
Coordination of Core Low-Power States at the Package Level
Package State
Core 1 State
Core 0 State
C0
C1¹
C2
C3
C4/C6
C0
Normal
Normal
Normal
Normal
Normal
C1
Normal
Normal
Normal
Normal
Normal
C2
Normal
Normal
Stop-Grant
Stop-Grant
C3
Normal
Normal
Stop-Grant
Deep Sleep
Stop-Grant Deep Sleep
C4/C6
Normal
Normal
Stop-Grant
Deep Sleep
Deeper Sleep/Intel®
Enhanced Deeper Sleep/
Intel® Deep Power-Down
NOTES:
1.
AutoHALT or MWAIT/C1.
2.1.1 Core Low-Power State Descriptions
2.1.1.1
2.1.1.2
Core C0 State
This is the normal operating state for cores in the processor.
Core C1/AutoHALT Power-Down State
C1/AutoHALT is a low-power state entered when a core executes the HALT instruction.
The processor core will transition to the C0 state upon occurrence of SMI#, INIT#,
LINT[1:0] (NMI, INTR), or FSB interrupt messages. RESET# will cause the processor to
immediately initialize itself.
A System Management Interrupt (SMI) handler will return execution to either Normal
state or the AutoHALT power-down state. See the Intel® 64 and IA-32 Architectures
Software Developer's Manuals, Volume 3A/3B: System Programmer's Guide for more
information.
The system can generate a STPCLK# while the processor is in the AutoHALT power-
down state. When the system deasserts the STPCLK# interrupt, the processor will
return execution to the HALT state.
Datasheet
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