X9000 Datasheet, PDF (27/77 Pages) Intel Corporation – Core2 Duo Processor and Core2 Extreme Processor on 45-nm Process

Electrical Specifications
3.5
Reserved and Unused Pins
All RESERVED (RSVD) pins must remain unconnected. Connection of these pins to V_CC,
V_SS, or to any other signal (including each other) can result in component malfunction
or incompatibility with future processors. See Section 4.2 for a pin listing of the
processor and the location of all RSVD pins.
For reliable operation, always connect unused inputs or bidirectional signals to an
appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if
AGTL+ termination is provided on the processor silicon. Unused active high inputs
should be connected through a resistor to ground (V_SS). Unused outputs can be left
unconnected.
The TEST1,TEST2,TEST3,TEST4,TEST5,TEST6,TEST7 pins are used for test purposes
internally and can be left as “No Connects”.
3.6
Table 3.
3.7
FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]). These signals should be connected to the clock chip and the appropriate
chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 3.
BSEL[2:0] Encoding for BCLK Frequency
BSEL[2] BSEL[1] BSEL[0] BCLK Frequency
L
L
L
RESERVED
L
L
H
RESERVED
L
H
H
166 MHz
L
H
L
200 MHz
H
H
L
RESERVED
H
H
H
RESERVED
H
L
H
RESERVED
H
L
L
RESERVED
FSB Signal Groups
The FSB signals have been combined into groups by buffer type in the following
sections. AGTL+ input signals have differential input buffers that use GTLREF as a
reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input
group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers
to the AGTL+ output group as well as the AGTL+ I/O group when driving. With the
implementation of a source synchronous data bus comes the need to specify two sets
of timing parameters. One set is for common clock signals which are dependent upon
the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the
source synchronous signals which are relative to their respective strobe lines (data and
address) as well as the rising edge of BCLK0. Asychronous signals are still present
(A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle.
Table 4 identifies which signals are common clock, source synchronous, and
asynchronous.
Datasheet
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