X9000 Datasheet, PDF (17/77 Pages) Intel Corporation – Core2 Duo Processor and Core2 Extreme Processor on 45-nm Process

Low Power Features
Warning:
2.1.2.6
2.1.2.6.1
2.1.2.6.2
Any transition on an input signal before the processor has returned to the Stop-Grant
state will result in unpredictable behavior.
Deeper Sleep State
The Deeper Sleep state is similar to the Deep Sleep state but further reduces core
voltage levels. One of the potential lower core voltage levels is achieved by entering the
base Deeper Sleep state. The Deeper Sleep state is entered through assertion of the
DPRSTP# pin while in the Deep Sleep state. The following lower core voltage level is
achieved by entering the Intel Enhanced Deeper Sleep state, which is a sub-state of the
Deeper Sleep state. Intel Enhanced Deeper Sleep state is entered through assertion of
the DPRSTP# pin while in the Deep Sleep only when the L2 cache has been completely
shut down. Refer to Section 2.1.2.6.1 and Section 2.1.2.6.3 for further details on
reducing the L2 cache and entering the Intel Enhanced Deeper Sleep state.
In response to entering Deeper Sleep, the processor drives the VID code corresponding
to the Deeper Sleep core voltage on the VID[6:0] pins. Refer to the platform design
guides for further details.
Exit from Deeper Sleep or the Intel Enhanced Deeper Sleep state is initiated by
DPRSTP# deassertion when either core requests a core state other than C4 or either
core requests a processor performance state other than the lowest operating point.
Intel® Enhanced Deeper Sleep State
Intel Enhanced Deeper Sleep state is a sub-state of Deeper Sleep that extends power
saving capabilities by allowing the processor to further reduce core voltage once the L2
cache has been reduced to zero ways and completely shut down. The following events
occur when the processor enters the Intel Enhanced Deeper Sleep state:
• The last core entering C4 issues a P_LVL4 or P_LVL5 I/O read or an MWAIT(C4)
instruction and then progressively reduces the L2 cache to zero.
• Once the L2 cache has been reduced to zero, the processor triggers a special
chipset sequence to notify the chipset to redirect all FSB traffic, except APIC
messages, to memory. The snoops are replied as misses by the chipset and are
directed to main memory instead of the L2 cache. This allows for higher residency
of the processor’s Intel Enhanced Deeper Sleep state.
• The processor drives the VID code corresponding to the Intel Enhanced Deeper
Sleep state core voltage on the VID[6:0] pins.
Intel® Deep Power-Down State (Previously known as Package C6 State)
When both cores have entered the CC6 state and the L2 cache has been shrunk down
to zero ways, the processor will enter the Intel Deep Power-Down state or C6 state. To
do so both cores save their architectural states in the on-die SRAM that resides in the
V_CCP domain. At this point, the core V_CC will be dropped to the lowest core voltage V_C6.
The processor is now in an extremely low-power state.
In the Intel Deep Power-Down state, the processor does not need to be snooped, as all
the caches are flushed before entering C6.
C6 exit is triggered by the chipset when it detects a break event. It deasserts the
DPRSTP#, DPSLP#, SLP#, and STPCLK# pins to exit the processor out of the C6 state.
At DPSLP# deassertion, the core V_CC ramps up to the LFM value and the processor
starts up its internal PLLs. At SLP# deassertion the processor is reset and the
architectural state is read back into the cores from an on-die SRAM. The restore will be
done in both cores irrespective of the break event and which core it is directed to. The
C6 exit event will put both cores in CC0.
Refer to Figure 3 and Figure 4 for C6 entry sequence and exit sequence.
Datasheet
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