X9000 Datasheet, PDF (18/77 Pages) Intel Corporation – Core2 Duo Processor and Core2 Extreme Processor on 45-nm Process

Low Power Features
Figure 3. C6 Entry Sequence
Core1
CC0
mwait C6
or Level 6
I/O Read
State
Save
CC6
Core0
CC0
mwait C6
or Level 6
I/O Read
L2
Shrink
State
Save
Level 6
I/O Read
CC6
Figure 4. C6 Exit Sequence
stpclk
assert
slp
assert
dpslp
assert
dprstp
assert
Package
C6
Core 0
Package
C6
dprst
deassert
dpsl
deassert
H/W
Reset
State
Restore
sl
deassert
State
Restore
ucode
reset
CC0
stpclk
deassert
ucode
reset
CC0
2.1.2.6.3
Core 1
Dynamic Cache Sizing
Dynamic Cache Sizing allows the processor to flush and disable a programmable
number of L2 cache ways upon each Deeper Sleep entry under the following
conditions:
• The second core is already in C4 and Intel Enhanced Deeper Sleep state or C6 state
is enabled (as specified in Section 2.1.1.6).
• The C0 timer that tracks continuous residency in the Normal package state has not
expired. This timer is cleared during the first entry into Deeper Sleep to allow
consecutive Deeper Sleep entries to shrink the L2 cache as needed.
• The FSB speed to processor core speed ratio is below the predefined L2 shrink
threshold.
If the FSB speed-to-processor core speed ratio is above the predefined L2 shrink
threshold, then L2 cache expansion will be requested. If the ratio is zero, then the ratio
will not be taken into account for Dynamic Cache Sizing decisions.
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Datasheet