X9000 Datasheet, PDF (66/77 Pages) Intel Corporation – Core2 Duo Processor and Core2 Extreme Processor on 45-nm Process

Package Mechanical Specifications and Pin Information
Table 14.
Signal Description (Sheet 5 of 8)
Name
Type
Description
IGNNE#
INIT#
LINT[1:0]
LOCK#
PRDY#
PREQ#
Input
Input
Input
Input/
Output
Output
Input
IGNNE# (Ignore Numeric Error) is asserted to force the processor
to ignore a numeric error and continue to execute non-control
floating-point instructions. If IGNNE# is deasserted, the processor
generates an exception on a non-control floating-point instruction if
a previous floating-point instruction caused an error. IGNNE# has
no effect when the NE bit in Control Register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition
of this signal following an input/output write instruction, it must be
valid along with the TRDY# assertion of the corresponding input/
output Write bus transaction.
INIT# (Initialization), when asserted, resets integer registers inside
the processor without affecting its internal caches or floating-point
registers. The processor then begins execution at the power-on
Reset vector configured during power-on configuration. The
processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal. However, to ensure
recognition of this signal following an input/output write instruction,
it must be valid along with the TRDY# assertion of the
corresponding input/output write bus transaction. INIT# must
connect the appropriate pins of both FSB agents.
If INIT# is sampled active on the active-to-inactive transition of
RESET#, then the processor executes its Built-in Self-Test (BIST).
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins
of all APIC Bus agents. When the APIC is disabled, the LINT0 signal
becomes INTR, a maskable interrupt request signal, and LINT1
becomes NMI, a nonmaskable interrupt. INTR and NMI are
backward compatible with the signals of those names on the
Pentium processor. Both signals are asynchronous.
Both of these signals must be software-configured via BIOS
programming of the APIC register space to be used either as NMI/
INTR or LINT[1:0]. Because the APIC is enabled by default after
Reset, operation of these pins as LINT[1:0] is the default
configuration.
LOCK# indicates to the system that a transaction must occur
atomically. This signal must connect the appropriate pins of both
FSB agents. For a locked sequence of transactions, LOCK# is
asserted from the beginning of the first transaction to the end of
the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of
the FSB, it will wait until it observes LOCK# deasserted. This
enables symmetric agents to retain ownership of the FSB
throughout the bus locked operation and ensure the atomicity of
lock.
Probe Ready signal used by debug tools to determine processor
debug readiness.
Probe Request signal used by debug tools to request debug
operation of the processor.
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