X9000 Datasheet, PDF (36/77 Pages) Intel Corporation – Core2 Duo Processor and Core2 Extreme Processor on 45-nm Process

Electrical Specifications
Table 10.
Table 11.
CMOS Signal Group DC Specifications
Symbol
Parameter
Min
V_CCP
V_IH
V_IL
V_OH
V_OL
I_OH
I_OL
I_LI
Cpad1
Cpad2
I/O Voltage
Input High Voltage
Input Low Voltage CMOS
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Input Leakage Current
Pad Capacitance
Pad Capacitance for CMOS
Input
1.00
0.7 * V_CCP
-0.10
0.9 * V_CCP
-0.10
1.5
1.5
—
1.80
0.95
Typ
1.05
V_CCP
0.00
V_CCP
0
—
—
—
2.30
1.2
Max
Unit Notes¹
1.10
V
V_CCP+0.1
V
0.3 * V_CCP V
V_CCP+0.1
V
0.1 * V_CCP V
4.1
mA
4.1
mA
±100
µA
2.75
pF
2
2, 3
2
2
5
4
6
7
1.45
pF
8
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
The V_CCP referred to in these specifications refers to instantaneous V_CCP.
3.
Refer to the processor I/O Buffer Models for I/V characteristics.
4.
Measured at 0.1*V_CCP.
5.
Measured at 0.9*V_CCP.
6.
For V_in between 0 V and V_CCP. Measured when the driver is tristated.z
7.
Cpad1 includes die capacitance only for DPRSTP#, DPSLP#, PWRGOOD. No package
parasitics are included.
8.
Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are
included.
Open Drain Signal Group DC Specifications
Symbol
Parameter
Min
V_OH
V_OL
I_OL
I_LO
Cpad
Output High Voltage
Output Low Voltage
Output Low Current
Output Leakage Current
Pad Capacitance
V_CCP – 5%
0
16
—
1.80
Typ
V_CCP
—
—
—
2.30
Max
Unit Notes¹
V_CCP + 5%
V
3
0.20
V
50
mA
2
±200
µA
4
2.75
pF
5
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Measured at 0.2 V.
3.
V_OH is determined by value of the external pull-up resistor to V_CCP. Refer to the appropriate
platform design guide for details.
4.
For V_in between 0 V and V_OH.
5.
Cpad includes die capacitance only. No package parasitics are included.
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Datasheet