IA80C152_10 Datasheet, PDF (8/61 Pages) InnovASIC, Inc – Universal Communications Controller

IA80C152
Universal Communications Controller
Data Sheet
July 29, 2010
The IA80C152 is partitioned into three major functional units identified as the C8051, the Direct
Memory Access (DMA) Controller, and the Global Serial Channel (GSC). The C8051 is
implemented using a CAST, Inc. Intellectual Property (IP) core. This core is instruction set
compatible with the 80C51BH, and contains compatible peripherals including a UART interface
and timers. The special function registers (SFRs) and interrupts are modified from the original
8051BH to accommodate the additional DMA controller and GSC peripherals.
The DMA Controller is a 2 channel, 8-bit device that is 16-bit addressable. Either channel can
access any combination of reads and writes to external memory, internal memory, or the SFR's.
Various modes allow the DMA to access the UART, GSC, SFRs, and internal and external
memory as well as provide for external control. Since there is only 1 data/program memory bus,
only one DMA channel or the microcontroller can have control at any given time. Arbitration
within the device makes this control transparent to the programmer.
The GSC is a serial interface that can be programmed to support CSMA/CD, SDLC, user
definable protocols, and limited HDLC. Protocol specific features are supported in hardware
such as address recognition, collision resolution, CRC generation and errors, automatic
re-transmission, and hardware acknowledge. The CSMA/CD protocol meets the requirements of
ISO/IEC 8802-3 and ANSI/IEEE Std 802.3 to the extent implemented in the original IC. The
SDLC protocol meets the requirements of IBM GA27-3093-04 to the extent implemented in the
original IC.
1.2 Features
Form, Fit, and Function Compatible with the Intel 80C152
Packaging options available in both standard and RoHS-Compliant:
– 68-Pin PLCC (plastic leaded chip carrier)
8051 Core with:
– Direct Memory Access (DMA)
– Global Serial Channel (GSC)
– MCS 51-compatible UART
– Two Timers/Counters
– Maskable Interrupts
Memory:
– 256 bytes internal RAM
– 64K bytes program memory
– 64K bytes data memory
5 or 7 I/O Ports
Up to 16.5-MHz Clock Frequency
Two-Channel DMA With Multiple Transfer Modes
GSC Provides Support for Multiple Protocols:
®
IA211040524-06
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