IA80C152_10 Datasheet, PDF (35/61 Pages) InnovASIC, Inc – Universal Communications Controller

IA80C152
Universal Communications Controller
Data Sheet
July 29, 2010
Table 20. P0*, P1*, P2*, P3*, P4*, P5, P6 Register
Port
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P0 Function Multiplexed Address/Data
Bit Address 087h 086h 085h 084h 083h 082h 081h 080h
P1 Function
– HLDAn HLDn RXCn TXCn DENn GTXD GRXD
Bit Address 097h 096h 095h 094h 093h 092h 091h 090h
P2 Function
Address and User Defined
Bit Address 0A7h 0A6h 0A5h 0A4h 0A3h 0A2h 0A1h 0A0h
P3 Function
RDn WRn T1
T0 INT1n INT0n TXD RXD
Bit Address 0B7h 0B6h 0B5h 0B4h 0B3h 0B2h 0B1h 0B0h
P4 Function
User Defined
Bit Address 0C7h 0C6h 0C5h 0C4h 0C3h 0C2h 0C1h 0C0h
P5 Function
User Defined
Bit Address
091h
P6 Function
User Defined
Address
0A1h
5.2.21 PCON (087h)
The Power Control register controls the power down and idle states of the IA80C152 as well as
various UART, GSC, and DMA functions as defined in Table 21.
Table 21. PCON Register
7
6
5
4
3
2
10
SMOD ARB REQ GAREN XRCLK GFIEN PD IDL
Bit [7]—SMOD → Doubles the baud rate of the UART if the bit is set to 1.
Bit [6]—ARB → The DMA (both channels) is put into Arbiter mode if the bit is set to 1.
Bit [5]—REQ → The DMA (both channels) is put into Requester mode if the bit is set
to 1.
Bit [4]—GAREN → The GSC Auxiliary Receive Enable allows the GSC to receive
back-to-back SDLC frames by setting the bit to 1. This bit has no effect in CSMA mode.
Bit [3]—XRCLK → Setting this bit enables the External Receive Clock to be used by the
receiver portion of the GSC.
Bit [2]—GFIEN → The GSC Flag Idle Enable bit generates idle flags between
transmitted SDLC frames when this bit is set to a 1. This bit has no effect in CSMA
mode.
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