IA80C152_10 Datasheet, PDF (40/61 Pages) InnovASIC, Inc – Universal Communications Controller

IA80C152
Universal Communications Controller
Data Sheet
July 29, 2010
Table 25. TCON* Register
7 6 5 4 3210
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Bit [7]—TF1 → Timer overFlow 1 interrupt flag set by hardware when timer 1
overflows. Hardware clears this flag when the processor vectors to the interrupt service
routine.
Bit [6]—TR1 → Timer Run 1 flag set by software to turn on timer 1 and cleared by
software to turn off timer 1.
Bit [5]—TF0 → Timer overFlow 0 interrupt flag set by hardware when timer 0
overflows. Hardware clears this flag when the processor vectors to the interrupt service
routine.
Bit [4]—TR0 → Timer Run 0 flag set by software to turn on timer 0 and cleared by
software to turn off timer 0.
Bit [3]—IE1 → Interrupt External 1 flag set by hardware when an edge is detected on
External Interrupt 1. Hardware clears this flag when the processor vectors to the interrupt
service routine.
Bit [2]—IT1 → Interrupt Type 1 flag is set by software to specify a falling edge triggered
interrupt for External Interrupt 1. The flag is cleared by software to specify a low level
triggered interrupt for External Interrupt 1.
Bit [1]—IE0 → Interrupt External 0 flag set by hardware when an edge is detected on
External Interrupt 0. Hardware clears this flag when the processor vectors to the interrupt
service routine.
Bit [0]—IT0 → Interrupt Type 0 flag is set by software to specify a falling edge triggered
interrupt for External Interrupt 0. The flag is cleared by software to specify a low level
triggered interrupt for External Interrupt 0.
5.2.34 TFIFO (085h)
This is the 3 byte buffer used for storing GSC transmit data. If TEN is set to a 1 transmission
begins as soon as data is written to TFIFO.
5.2.35 TH0, TL0 (08Ch, 08Ah)
These registers provide the high byte (TH0) and low byte (TL0) values for Timer 0. These
registers may be used together or separately depending on Timer 0 mode bits.
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