IA80C152_10 Datasheet, PDF (28/61 Pages) InnovASIC, Inc – Universal Communications Controller

IA80C152
Universal Communications Controller
Data Sheet
July 29, 2010
5.2.3 AMSK0,1 (0D5h, 0E5h)
Address Match Mask registers are used to set the corresponding bit in Address match registers to
don’t care. Setting the bit to a one in the AMSK register sets the corresponding bit in the ADR
register to don’t care.
5.2.4 B* (0F0h)
The B register used for multiply and divide instructions. May also be used as a general purpose
register.
5.2.5 BAUD (094h)
Contains the value to be used by the baud rate determining equation. The value written to
BAUD will actually be stored in a reload register. When the BAUD register contents are
decremented to 00H the BAUD register will be reloaded from the reload register. Reading the
BAUD register yields the current baud rate timer value. A read during a GSC operation may not
give the current value because the value in BAUD could decrement after it is read and before the
read value can be stored in its destination. BAUD rate = Fosc/((BAUD + 1)*8)
5.2.6 BCRL0, BCRH0 (0E2h, 0E3h)
Byte count register low and high bytes for DMA channel 0. The two registers provide a 16-bit
value representing the number of DMA transfers via channel 0. Valid count range is from 0
to 65535.
5.2.7 BCRL1, BCRH1 (0F2h, 0F3h)
Byte count register low and high bytes for DMA channel 1. The two registers provide a 16-bit
value representing the number of DMA transfers via channel 1. Valid count range is from 0
to 65535.
5.2.8 BKOFF (0C4h)
An 8 bit count down timer with a clock period equal to one slot time. A user may read the
register, but the register is clocked asynchronously to the CPU so invalid data can result.
Writing to BKOFF will have no effect.
5.2.9 DARL0, DARH0 (0C2h, 0C3h)
Destination address register low and high bytes for DMA channel 0. The two registers provide a
16-bit value representing the address of the destination for a DMA transfer via channel 0. Valid
address range is from 0 to 65535.
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