IA80C152_10 Datasheet, PDF (43/61 Pages) InnovASIC, Inc – Universal Communications Controller

IA80C152
Universal Communications Controller
Data Sheet
July 29, 2010
Power Down Mode is entered through software control of the PCON register. Power Down
disables the oscillator causing all functions to stop. RAM data is maintained because power is
not removed from the device. The only way to exit power down mode is to invoke a hardware
reset.
Table 28. Power Conservation Modes
Program
Port Port Port Port Port ^{Port Port}
Mode Fetch ALE PSENn EPSENn^a 0
1
2
3
4
5^a
6^a
Idle P0, P2
1
1
1
Float Data Addr. Data Data Data Data
P5, P6^{a 1}
1
1
Data Data Data Data Data 0FFh Addr.
Power P0, P2
0
0
1
Float Data Data Data Data Data Data
Down _{P5, P6}^a 0
1
0
Data Data Data Data Data 0FFh 0FFh
a_{JB and JD versions only.}
5.4 Oscillator Pins
There are 2 methods for providing a clock to the IA80C152. One method is to provide a crystal
oscillator and the other method is to provide an external clock source. When providing a crystal
oscillator, the XTAL1 pin is the input and XTAL2 is the output. The min and max crystal
frequencies are 3.5 and 16.5 MHz, respectively.
When providing an external clock source, XTAL1 is the input and XTAL2 has no connection.
Duty cycle does not matter to the device, however, the external clock source requires a minimum
pulse width of 20 ns.
Figures 6 through 13 present the external program memory read cycle, the external data memory
read cycle, the external data memory write cycle, the external clock drive waveform, the shift
register mode timing waveforms, the GSC receiver timings (internal baud rate generator), the
GSC transmit timings (internal baud rate generator), the GSC timings (external clock)
respectively. Tables 29 through 32 present the external clock drive, the local serial channel
timing—shift register mode, the global serial port timing—internal baud rate generator, and the
global serial port timing—external clock, respectively.
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