IA80C152_10 Datasheet, PDF (37/61 Pages) InnovASIC, Inc – Universal Communications Controller

IA80C152
Universal Communications Controller
Data Sheet
July 29, 2010
Bit [0]—P → Parity flag set or cleared by the hardware each instruction to indicate odd
or even number of 1s in the accumulator.
5.2.24 RFIFO (0F4h)
This is a three-byte buffer which points to the oldest data in the buffer. The buffer is loaded with
receive data every time the GSC receiver receives a new byte of data.
5.2.25 RSTAT* (0E8h)
This register provides status of the GSC receiver as defined in Table 23.
Table 23. RSTAT* Register
7
6
5
4
3
2
1
0
OVR RCABT AE CRCE RDN RFNE GREN HABEN
Bit [7]—OVR → This bit is set by the GSC to indicate that the receive FIFO was full and
then new data was shifted into it. AE and /or CRCE may also be set. This flag is cleared
by the user.
Bit [6]—RCABT → This bit is set by the GSC when a collision is detected after data has
been loaded into the receive FIFO in CSMA/CD mode. In SDLC mode this bit indicates
that 7 consecutive 1s were detected before an end flag but after data was loaded into the
receive FIFO. AE may also be set.
Bit [5]—AE → This bit is set by the GSC in CSMA/CD mode to indicate that the
receiver shift register is not full and the CRC is bad when the EOF was detected. If the
CRC is correct AE will not be set and a misalignment will be assumed to be caused by
―dribble bits‖ as the line went idle. In SDLC mode AE is set if a non-byte aligned flag is
received. CRCE may also be set.
Bit [4]—CRCE → This bit is controlled by the GSC and if set indicates that a properly
aligned frame was received with a mismatched CRC.
Bit [3]—RDN → This bit is controlled by the GSC and if set indicates a successful
receive operation has occurred. This bit will not be set if a CRC, alignment, abort, or
FIFO overrun error occurred.
Bit [2]—RFNE → This bit if set indicates that the receive FIFO is not empty. This flag is
controlled by the GSC. If all the data is read from the FIFO the GSC will clear the bit.
Bit [1]—GREN → When this bit is set the receiver is enabled to accept incoming frames.
RFIFO should be cleared before setting this bit by reading RFIFO until RFNE = 0. This
should be done because setting GREN to a 1 clears RFIFO. It takes twelve clock cycles
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