IA80C152_10 Datasheet, PDF (58/61 Pages) InnovASIC, Inc – Universal Communications Controller

IA80C152
Universal Communications Controller
Data Sheet
July 29, 2010
9. Errata
The following errata are associated with all versions of the IA80C152. A workaround to the
identified problem has been provided where possible.
9.1 Errata Summary
Table 36 presents a summary of errata.
Table 36. Summary of Errata
Errata
No.
1
Problem
Under certain circumstances, the DMA arbiter will ―lock up‖ in alternate
cycles mode. This problem occurs when one DMA channel has finished
performing a transfer and another DMA initiates a transfer with the byte
Count Register having been set to 0001 by the CPU.
Rev.
01
Exists
2 Original Intel device has a linear resistor as the pullup on input RESET.
Exists
3 DMA can interfere with processing of interrupts of different priority.
Exists
4 Corruption of read data may occur if Port 0 bit written to 0.
Exists
9.2 Errata Detail
Errata No. 1
Problem: Under certain circumstances, the DMA arbiter will ―lock up‖ in alternate cycles
mode. This problem occurs when one DMA channel has finished performing a transfer and
another DMA initiates a transfer with the byte Count Register having been set to 0001 by the
CPU.
Workaround: Avoid using the alternate cycles DMA mode in conjunction with a byte count of
one.
Errata No. 2
Problem: Original Intel device has a linear resistor as the pullup on input RESET.
Workaround: None. A non-linear resistor is on the Innovasic device. This may affect
operation of certain R/C reset circuits.
®
IA211040524-06
http://www.Innovasic.com
UNCONTROLLED WHEN PRINTED OR COPIED
Customer Support:
Page 58 of 61
1-888-824-4184