IA80C152_10 Datasheet, PDF (3/61 Pages) InnovASIC, Inc – Universal Communications Controller

IA80C152
Universal Communications Controller
Data Sheet
July 29, 2010
TABLE OF CONTENTS
List of Figures ..................................................................................................................................5
List of Tables ...................................................................................................................................6
1. Introduction.............................................................................................................................7
1.1 General Description.......................................................................................................7
1.2 Features .........................................................................................................................8
2. Packaging, Pin Descriptions, and Physical Dimensions.........................................................9
2.1 Packages and Pinouts ....................................................................................................9
2.1.1 JA/JC...............................................................................................................10
2.1.2 JB/JD...............................................................................................................13
2.1.3 Physical Dimensions.......................................................................................16
2.2 I/O Signal Description.................................................................................................17
3. Maximum Ratings, Thermal Characteristics, and DC Parameters .......................................20
4. Device Architecture ..............................................................................................................22
4.1 Functional Block Diagram ..........................................................................................22
4.2 Memory Space.............................................................................................................23
5. Peripheral Architecture .........................................................................................................25
5.1 Registers and Interrupts...............................................................................................25
5.2 Register Set Descriptions ............................................................................................27
5.2.1 A* (0E0h) .......................................................................................................27
5.2.2 ADR0,1,2,3 (095h, 0A5h, 0B5h, 0c5h) ..........................................................27
5.2.3 AMSK0,1 (0D5h, 0E5h).................................................................................28
5.2.4 B* (0F0h)........................................................................................................28
5.2.5 BAUD (094h) .................................................................................................28
5.2.6 BCRL0, BCRH0 (0E2h, 0E3h) ......................................................................28
5.2.7 BCRL1, BCRH1 (0F2h, 0F3h) .......................................................................28
5.2.8 BKOFF (0C4h) ...............................................................................................28
5.2.9 DARL0, DARH0 (0C2h, 0C3h) .....................................................................28
5.2.10 DARL1, DARH1 (0D2h, 0D3h).....................................................................29
5.2.11 DCON0,1 (092h, 093h) ..................................................................................29
5.2.12 DPL, DPH (082h, 083h) .................................................................................30
5.2.13 GMOD (084h) ................................................................................................30
5.2.14 IE* (0A8h) ......................................................................................................31
5.2.15 IEN1* (0C8h) .................................................................................................32
5.2.16 IFS (0A4h) ......................................................................................................32
5.2.17 IP* (0B8h) ......................................................................................................33
5.2.18 IPN1* (0F8h) ..................................................................................................33
5.2.19 MYSLOT (0F5h) ............................................................................................34
5.2.20 P0*, P1*, P2*, P3*, P4*, P5, P6 (080h, 090h, 0A0h, 0Boh, 0C0h,
091h, 0A1h) ....................................................................................................34
5.2.21 PCON (087h) ..................................................................................................35
5.2.22 PRBS (0E4h) ..................................................................................................36
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