IA80C152_10 Datasheet, PDF (33/61 Pages) InnovASIC, Inc – Universal Communications Controller

IA80C152
Universal Communications Controller
Data Sheet
July 29, 2010
5.2.17 IP* (0B8h)
The Interrupt Priority register allows the software to select which interrupts have a higher than
normal priority. If a bit is 0, the interrupt has normal priority. If a bit is 1, the interrupt has a
higher priority. When multiple bits are set to higher priority, interrupts are resolved in the same
order as their normal priority setting (see Table 17).
Table 17. IP* Register
7
6
5
43 2 1 0
Reserved Reserved Reserved PS PT1 PX1 PT0 PX0
Bit [7]—Reserved.
Bit [6]—Reserved.
Bit [5]—Reserved.
Bit [4]—PS → Set normal or high priority level for serial port interrupt.
Bit [3]—PT1 → Set normal or high priority level for Timer 1 overflow interrupt.
Bit [2]—PX1 → Set normal or high priority level for External Interrupt 1.
Bit [1]—PT0 → Set normal or high priority level for Timer 0 overflow interrupt.
Bit [0]—PX0 → Set normal or high priority level for External Interrupt 0.
5.2.18 IPN1* (0F8h)
The Interrupt Priority Number 1 register allows the software to select which interrupts have a
higher than normal priority. If a bit is 0, the interrupt has normal priority. If a bit is 1, the
interrupt has a higher priority. When multiple bits are set to higher priority, interrupts are
resolved in the same order as their normal priority setting (see Table 18).
Table 18. IPN1* Register
7
6
5
4
3
2
1
0
Reserved Reserved PGSTE PDMA1 PGSTV PDMA0 PGSRE PGSRV
Bit [7]—Reserved.
Bit [6]—Reserved.
Bit [5]—PGSTE → Set normal or high priority level for GSC Transmit Error interrupt.
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