IA80C152_10 Datasheet, PDF (30/61 Pages) InnovASIC, Inc – Universal Communications Controller

IA80C152
Universal Communications Controller
Data Sheet
July 29, 2010
Bit [2]—TM → If DM is 1, TM selects if DMA is initiated by an external signal (TM=1)
or by a serial port bit (TM=0). If DM is 0, TM selects whether DMA transfers are in
burst mode (TM=1) or in alternate cycles mode (TM=0).
DM TM Mode
0 0 Alternate Cycles
0 1 Burst
1 0 LSC/GSC Interrupt Demand
1 1 External Interrupt Demand
Bit [1]—DONE → This bit indicates that the DMA operation has completed. It also
causes an interrupt. This bit is set to 1 when BCRn equals 0 and is set to 0 when the
interrupt is vectored. The user can also set and clear this bit.
Bit [0]—GO → If this bit is set to 1, it enables the DMA channel.
5.2.12 DPL, DPH (082h, 083h)
DPTR, or the ―data pointer‖ consists of the two 8-bit registers, DPL and DPH. The DPTR must
be used for accesses to external memory requiring 16-bit addresses.
5.2.13 GMOD (084h)
An 8-bit register that controls the GSC Modes as described in Table 14.
Table 14. GMOD Register
7
6 543 2 1 0
XTCLK M1 M0 AL CT PL1 PL0 PR
Bit [7]—XTCLK → This bit enables the use of an external transmit clock. A 1 enables
the external clock (input on port 1, bit 3), a zero enables the internal baud rate generator.
Bits [6–5]—M1, M0 → These bits are the backoff mode and test mode select bits as
defined in the following table.
M1 M0 Mode
0 0 Normal
0 1 Raw Transmit
1 0 Raw Receive
1 1 Alternate Backoff
In Raw Receive mode the transmitter operates normally. The receiver operates normally
except that all the bytes following the BOF are loaded into the receive FIFO including the
CRC.
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