IA80C152_10 Datasheet, PDF (22/61 Pages) InnovASIC, Inc – Universal Communications Controller

IA80C152
Universal Communications Controller
Data Sheet
July 29, 2010
4. Device Architecture
4.1 Functional Block Diagram
Figure 4 shows the major functional blocks of the IA80C152. Each version of the IA80C152
function identically to each other with the exception of the 2 additional I/O ports (Port 5 and
Port 6) in the JB and JD versions.
I/O for Memory, GSC, DMA, UART, Interrupts, and Timers
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Memory
Control
XTAL
Reset
Clock Gen.
& Timing
256x8 RAM
C8051
CPU
Control
Address/Data
UART
Interrupts
Timers
DMA
GSC
= JB and JD versions only.
Figure 4. Functional Block Diagram
®
IA211040524-06
http://www.Innovasic.com
UNCONTROLLED WHEN PRINTED OR COPIED
Customer Support:
Page 22 of 61
1-888-824-4184