IA80C152_10 Datasheet, PDF (41/61 Pages) InnovASIC, Inc – Universal Communications Controller

IA80C152
Universal Communications Controller
Data Sheet
July 29, 2010
5.2.36 TH1, TL1 (08Dh, 08Bh)
These registers provide the high byte (TH0) and low byte (TL0) values for Timer 0. These
registers may be used together or separately depending on Timer 0 mode bits.
5.2.37 TMOD (089h)
This register controls the set up and modes of Timers 0 and 1 as defined by Table 26.
Table 26. TMOD Register
7
6 54
3
2 10
Timer 1
Timer 0
GATE C/Tn M1 M0 GATE C/Tn M1 M0
Bits [7,3]—GATE → When this bit is set, Timers/Counters may be turned on or off by
the corresponding External Interrupt being high, if the appropriate TR bit is set. When
this bit is cleared, Timers/Counters may only be turned on or off by the appropriate TR
bit.
Bits [6,2]—C/Tn → Counter/Timer flag. Set by software for Counter operation, cleared
by software for Timer operation.
Bit [5,4,1,0]—M1, M0 → Set the mode of the Timers/Counters as defined by the table
below.
Mode M1 M0
Description
0 0 0 8-bit Timer (THx) with 5-bit Prescalar (TLx)
1 0 1 16-bit Timer/Counter (THx cascaded with TLx)
2 1 0 8-bit Auto Reload Timer/Counter (THx), Reload Value (THx)
3 1 1 One 8-bit Timer/Counter (TL0) controlled by Timer 0 control bits.
One 8-bit Timer/Counter (TH0) controlled by Timer 1 control bits. Timer 1 is
stopped.
5.2.38 TSTAT* (0D8h)
This register provides status of the GSC transmitter as defined by Table 27.
Table 27. TMOD Register
7
6
5
4
3
2
1
0
LNI NOACK UR TCDT TDN TFNF TEN DMA
Bit [7]—LNI → The GSC sets this bit to indicate that the receive line is idle. In
CSMA/CD mode LNI is set if GRXD remains high for ~ 1.6 bit times. LNI is cleared
after a transition on GRXD. In SDLC node LNI is set if 15 consecutive ones are
received.
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