IA80C152_10 Datasheet, PDF (34/61 Pages) InnovASIC, Inc – Universal Communications Controller

IA80C152
Universal Communications Controller
Data Sheet
July 29, 2010
Bit [4]—PDMA1 → Set normal or high priority level for DMA channel 1 interrupt.
Bit [3]—PGSTV → Set normal or high priority level for GSC Transmit Valid interrupt.
Bit [2]—PDMA0 → Set normal or high priority level for DMA channel 0 interrupt.
Bit [1]—PGSRE → Set normal or high priority level for GSC Receive Error interrupt.
Bit [0]—PGSRV → Set normal or high priority level for GSC Receive Valid interrupt.
5.2.19 MYSLOT (0F5h)
Register that controls the slot address for the devices as well as the type of Jam used and which
backoff algorithm is used during a collision (see Table 19).
Table 19. MYSLOT Register
7
6
5
4
3
21
0
DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0
Bit [7]—DCJ → A 1 selects DC type jam. A 0 selects AC type jam.
Bit [6]—DCR → The Deterministic Collision Resolution register determines which
resolution algorithm to use. Setting this bit to a 1 selects the deterministic resolution
algorithm. The user must initialize TCDCNT with the maximum number of slots that are
appropriate for the system. To disable the PBRS this register must be set to all 1s. If
DCR is cleared to 0 then a random slot assignment is used. The type of random backoff
used is selected by bits M1, M0 of the GMOD register.
Bits [5–0]—SA5–SA0 → The six-slot address bits determine not only the address but
also the priority. Addresses 0 through 63 are available with 63 having the highest priority
and 1 the lowest. An address of 0 will prevent a station from transmitting during the
collision resolution period.
5.2.20 P0*, P1*, P2*, P3*, P4*, P5, P6 (080h, 090h, 0A0h, 0Boh, 0C0h, 091h, 0A1h)
These registers are for I/O as defined in Table 20. Most registers have a dual function. P5 and
P6 are not bit addressable and are only available in the JB and JD versions of the IC.
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