IA80C152_10 Datasheet, PDF (36/61 Pages) InnovASIC, Inc – Universal Communications Controller

IA80C152
Universal Communications Controller
Data Sheet
July 29, 2010
Bit [1]—PD → The Power Down bit puts the IA80C152 into the power down power
saving mode by setting this bit to a 1.
Bit [0]—IDL → The Idle bit puts the IA80C152 into the idle power saving mode by
setting this bit to a 1.
5.2.22 PRBS (0E4h)
This register contains the pseudo-random number to be used in the CSMA/CD backoff
algorithm. The number is generated by using a feedback shift register clocked by the CPU phase
clocks. Writing all 1s to this register will cause the register to freeze at all 1s. Writing any other
value to it will cause it to start again. A read of this register will not always give the seed value
due to the register being clocked by the CPUs phase clocks.
5.2.23 PSW* (0D0h)
The Program Status Word register provides arithmetic and other microcontroller status as well as
control for the selection of register banks 0 through 4 (see Table 22).
Table 22. PSW* Register
7 65 4
32
1
0
CY AC F0 RS1 RS0 OV Reserved P
Bit [7]—CY → Carry Flag set to 1 if an instruction execution results in a carry/borrow
from/to bit 7.
Bit [6]—AC → Auxiliary Carry Flag set to 1 if an instruction execution results in a
carry/borrow from/to bit 3.
Bit [5]—F0 → Flag 0 available for user defined general purpose.
Bits [4–3]—RS1, RS0 → Register bank Select 1 bit and Register bank Select 0 bit in
combination define the current register bank to be used by the microprocessor. See table
below.
Register Bank RS1 RS0 Register Bank Addresses
0
00
00h-07h
1
01
08h-0Fh
2
10
10h-17h
3
11
18h-1Fh
Bit [2]—OV → The Overflow bit indicates an arithmetic overflow when set to a 1.
Bit [1]—Reserved.
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