IA80C152_10 Datasheet, PDF (32/61 Pages) InnovASIC, Inc – Universal Communications Controller

IA80C152
Universal Communications Controller
Data Sheet
July 29, 2010
Bit [4]—ES → Enable or disable serial port interrupt.
Bit [3]—ET1 → Enable or disable Timer 1 overflow interrupt.
Bit [2]—EX1 → Enable or disable External Interrupt 1.
Bit [1]—ET0 → Enable or disable Timer 0 overflow interrupt.
Bit [0]—EX0 → Enable or disable External Interrupt 0.
5.2.15 IEN1* (0C8h)
The Interrupt Enable Number 1 register allows the software to select which interrupts are
enabled as shown in Table 16. If a bit is 0, the interrupt is disabled. If a bit is 1, the interrupt is
enabled.
Table 16. IEN1* Register
7
6
5
4
3
2
1
0
Reserved Reserved EGSTE EDMA1 EGSTV EDMA0 EGSRE EGSRV
Bit [7]—Reserved.
Bit [6]—Reserved.
Bit [5]—EGSTE → Enable or disable GSC Transmit Error interrupt.
Bit [4]—EDMA1 → Enable or disable DMA channel 1 interrupt.
Bit [3]—EGSTV → Enable or disable GSC Transmit Valid interrupt.
Bit [2]—EDMA0 → Enable or disable DMA channel 0 interrupt.
Bit [1]—EGSRE → Enable or disable GSC Receive Error interrupt.
Bit [0]—EGSRV → Enable or disable GSC Receive Valid interrupt.
5.2.16 IFS (0A4h)
The Interframe Spacing register determines the number of bit times between transmitted frames
in both CSMA/CD and SDLC. Only even bit times can be used. The number written to this
register is divided by two and loaded into the seven most significant bits. An interframe space is
created by counting down this seven bit number twice. The value read from this register is the
current count value in the upper seven bits and the first or second count down in the LSB. A 1
indicates the first count down and a 0 indicates the second count down. The value may not be
valid because the register is clocked asynchronously to the CPU.
®
IA211040524-06
http://www.Innovasic.com
UNCONTROLLED WHEN PRINTED OR COPIED
Customer Support:
Page 32 of 61
1-888-824-4184