IA80C152_10 Datasheet, PDF (29/61 Pages) InnovASIC, Inc – Universal Communications Controller

IA80C152
Universal Communications Controller
Data Sheet
July 29, 2010
5.2.10 DARL1, DARH1 (0D2h, 0D3h)
Destination address register low and high bytes for DMA channel 1. The two registers provide a
16-bit value representing the address of the destination for a DMA transfer via channel 1. Valid
address range is from 0 to 65535.
5.2.11 DCON0,1 (092h, 093h)
DCON0 and DCON1 control DMA channel 0 or 1, respectively. Each bit in these 8-bit registers
control the DMA transfer as described in Table 13.
Table 13. DCON0,1 Register
7 6 5 432
1
0
DAS IDA SAS ISA DM TM DONE GO
Bit [7]—DAS → This bit in conjunction with IDA determines the destination address
space.
Bit [6]—IDA → If IDA is set to 1 then the destination address is automatically
incremented after the transfer of each byte.
DAS IDA Destination Auto-Increment
0 0 External Ram NO
0 1 External Ram YES
1 0 SFR
NO
1 1 Internal RAM YES
Bit [5]—SAS → This bit in conjunction with ISA determines the source address space.
Bit [4]—ISA → If ISA is set to 1, the source address is automatically incremented after
the transfer of each byte.
SAS ISA Source
Auto-Increment
0 0 External Ram NO
0 1 External Ram YES
1 0 SFR
NO
1 1 Internal RAM YES
Bit [3]—DM → If this bit is set to 1, the DMA channel operates in demand mode. In this
mode the DMA is initiated by either an external signal or by a serial port flag depending
on the value of the TM bit. If the DM bit is set to 0, DMA is initiated by setting the GO
bit.
®
IA211040524-06
http://www.Innovasic.com
UNCONTROLLED WHEN PRINTED OR COPIED
Customer Support:
Page 29 of 61
1-888-824-4184