IA80C152_10 Datasheet, PDF (38/61 Pages) InnovASIC, Inc – Universal Communications Controller

IA80C152
Universal Communications Controller
Data Sheet
July 29, 2010
for the status of RFNE to be updated after a read of RFIFO. Setting GREN also clears
RDN, CRCE, AE and RCABT. GREN is cleared by hardware at the end of a reception
or if receive errors are encountered. The user is responsible for setting this bit to a 1.
The user or the GSC can set this bit to a 0. In CSMA/CD mode the status of GREN has
no effect on whether the receiver detects a collision because the receiver always
monitors the receive pin.
Bit [0]—HABEN → The Hardware Based Acknowledge Enable when set to a 1 enables
this feature.
5.2.26 SARL0, SARH0 (0A2h, 0A3h)
Source address register low and high bytes for DMA channel 0. The two registers provide a
16-bit value representing the address of the source for a DMA transfer via channel 0. Valid
address range is from 0 to 65535.
5.2.27 SARL1, SARH1 (0B2h, 0B3h)
Source address register low and high bytes for DMA channel 1. The two registers provide a
16-bit value representing the address of the source for a DMA transfer via channel 1. Valid
address range is from 0 to 65535.
5.2.28 SBUF (099h)
Writes to this register load the transmit register, and reads access the receive register of the LSC.
5.2.29 SCON* (098h)
This register controls the set up of the UART as defined by Table 24.
Table 24. SCON* Register
7
6
5
4
3
2 10
SM0 SM1 SM2 REN TB8 RB8 TI RI
Bits [7–6]—SM0, SM1 → The combination of these 2 bits controls the mode and type of
baud rate.
Mode
0
1
2
3
SM0
0
0
1
1
SM1
0
1
0
1
Description
Shift Register
8-bit UART
9-bit UART
9-bit UART
Baud Rate
(Osc. Freq.)/12
Variable
(Osc. Freq.)/64 or (Osc. Freq.)/32
Variable
®
IA211040524-06
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