IA80C152_10 Datasheet, PDF (59/61 Pages) InnovASIC, Inc – Universal Communications Controller

IA80C152
Universal Communications Controller
Data Sheet
July 29, 2010
Errata No. 3
Problem: DMA can interfere with processing of interrupts of different priority.
Description: The following sequence of events must occur for this issue to occur:
1. A low-priority (associated priority bit not set) interrupt is accepted by the processor, but
vector fetch is delayed by a DMA cycle.
2. During DMA cycle, a high-priority (associated priority bit set) interrupt is accepted.
3. After DMA cycle, the high-priority vector is fetched. No further processing of any low-
priority interrupts will occur.
Workaround: Use inherent prioritization of interrupts (all interrupts set to high or low priority
only) if DMA is enabled.
Errata No. 4
Problem: Corruption of read data may occur if Port 0 bit written to 0.
Description: If any bit in Port 0 is written to a 0 while the device is configured to use P0 as
address/data bus, corruption of read data may occur.
Workaround: Write all Port 0 register bits to a 1 while using P0 as address/data bus.
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