IA80C152_10 Datasheet, PDF (42/61 Pages) InnovASIC, Inc – Universal Communications Controller

IA80C152
Universal Communications Controller
Data Sheet
July 29, 2010
Bit [6]—NOACK → The GSC sets this bit to indicate that an acknowledge was not
received for the previous frame. This bit will be set only if HABEN is set and no
acknowledge is received before the end of the IFS. NOACK will not be set following a
broadcast or a multi-cast packet.
Bit [5]—UR → The GSC sets this bit to indicate that in DMA mode the last bit was
shifted out of the transmit register and that the DMA byte count did not equal 0. When
this occurs the transmitter stops without sending the CRC and the end flag.
Bit [4]—TCDT → The GSC sets this bit to indicate that the transmission stopped due to a
collision. The bit is set by a collision occurring during the data, the CRC or if there are
more than 8 collisions.
Bit [3]—TDN → The GSC sets this bit to indicate that a frame transmission completed
successfully. If HABEN is set, TDN will not be set until the end of the IFS so that the
acknowledge can be checked. TDN will not be set if an acknowledge is expected but not
received. An acknowledge will not be expected after a broadcast or a multi-cast packet.
Bit [2]—TFNF → If this bit is a 1 TFIFO is not full and new data may be written to it.
Bit [1]—TEN → When TEN is set it will cause TDN, UR, TCDT and NOACK to be
reset and the TFIFO to be cleared. The transmitter will clear TEN after a successful
transmission, a collision during data, CRC or end flag. The user sets the bit and the user
of the GSC can clear the bit. If the bit is cleared during a transmission the transmit pin
goes to a high level. This is the method used to send an abort character in SDLC. DEN
is also forced to a high level. An end of transmission occurs whenever the TFIFO is
emptied.
Bit [0]—DMA → If this bit is set it indicates that the DMA channels are used to service
the RFIFO and TFIFO and that GSC interrupts occur on TDN and RDN. If set it also
enables UR to become set. If this bit is cleared it indicates that the GSC is operating in
normal mode and interrupts occur on TFNF and RFNE.
5.3 Power Conservation Modes
There are 2 power conservation modes identified as Idle Mode and Power Down Mode. The
IA80C152 pins will have values according to the Table 28 below.
Idle Mode is entered through software control of the PCON register. Idle halts processor
execution and the DMA. The GSC continues to operate to the extent that it can without the
processor or DMA servicing its requests. Idle mode is exited upon receipt of any enabled
interrupt or invoking a hardware reset.
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