IA80C152_10 Datasheet, PDF (39/61 Pages) InnovASIC, Inc – Universal Communications Controller

IA80C152
Universal Communications Controller
Data Sheet
July 29, 2010
Bit [5]—SM2 → When this bit is set and the UART mode is 1, RI will not be activated
unless a valid stop bit is received. When this bit is set and the UART mode is 2 or 3, RI
will not be activated if the 9th bit is 0. In mode 0 SM2 should be set to 0.
Bit [4]—REN → Setting this bit enables the UART to receive. Clearing this bit disables
UART reception.
Bit [3]—TB8 → In modes 2 and 3, the value of this bit is transmitted during the 9th bit
time. This bit is set or cleared by software.
Bit [2]—RB8 → In modes 2 and 3, this bit is the value of the 9th bit that was received by
the UART. In mode 1 with SM2 = 1, this bit is the value of the stop bit received by the
UART. In mode 0 RB8 is not used.
Bit [2]—TI → Transmit Interrupt flag set by hardware at the end of the 8th bit in mode 0
or at the beginning of the stop bit in modes 1, 2, or 3. This bit must be cleared by
software to clear the interrupt.
Bit [0]—RI → Receive Interrupt flag set by hardware at the end of the 8th bit in mode 0
or halfway through the stop bit in modes 1, 2, or 3. This bit must be cleared by software
to clear the interrupt.
5.2.30 SLOTTM (0B4h)
Determines the length of the slot time in CSMA/CD mode. A slot time equals SLOTTM *
(1/baud rate). Reads from this location are unreliable because this register is clocked
asynchronously to the CPU. Loading a value of 0 results in a slot time of 256 bit times.
5.2.31 SP (081h)
This register is the stack pointer. Its value points to the memory location that is the beginning of
the stack.
5.2.32 TCDCNT (0D4h)
If probabilistic CSMA/CD is used this register contains the number of collisions. The user must
clear this register before transmitting a new frame so the GSC can distinguish between a new
frame and the retransmit of a frame. In deterministic backoff mode TCDCNT is used to hold the
maximum number of slots.
5.2.33 TCON* (088h)
This register controls the operation of the Timers 0 and 1 and External Interrupts 0 and 1 as
defined by Table 25.
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