IA80C152_10 Datasheet, PDF (31/61 Pages) InnovASIC, Inc – Universal Communications Controller

IA80C152
Universal Communications Controller
Data Sheet
July 29, 2010
In the Raw Transmit mode the receiver operates as normal and zero bit detection is
performed in SDLC mode. The transmit output is internally connected to the receiver
input for loopback testing. Data transmitted is done so without a preamble, flag or zero
bit insertion and without a CRC.
In the Alternate Backoff mode the backoff is modified so it is delayed until the end of the
IFS. Since the IFS time is generally longer than the slot time this should help to prevent
collisions.
Bit [4]—AL → This bit determines the address length used. If set to a 1, the 16-bit
addressing is used. If set to a 0, the 8 bit addressing is used.
Bit [3]—CT → This bit determines the CRC type used. If set to a 1, the 32-bit
AUTODIN II-32 is used. If set to a 0, the 16 bit CRC-CCITT is used.
Bits [2–1]—PL0, PL1 → Preamble length:
PL1 PL0 Preamble length in bits
00
0
01
8
10
32
11
64
The length noted in the table includes the two-bit BOF in CSMA/CD mode but not the
SDLC flag. Zero length preamble is not compatible with CSMA/CD mode.
Bit [0]—PR → If set to a 1, the GSC is in SDLC mode. If set to a 0, the GSC is in
CSMA/CD mode.
5.2.14 IE* (0A8h)
The Interrupt Enable register allows the software to select which interrupts are enabled as shown
in Table 15. If a bit is 0, the interrupt is disabled. If a bit is 1, the interrupt is enabled.
Table 15. IE* Register
7
6
5
43 2 1 0
EA Reserved Reserved ES ET1 EX1 ET0 EX0
Bit [7]—EA → Enable All interrupts. This bit globally enables or disables all interrupts
regardless of the state of the individual bits.
Bit [6]—Reserved.
Bit [5]—Reserved.
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