ICS1893 Datasheet, PDF (99/152 Pages) Integrated Circuit Systems – 3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

ICS1893 - Release
Chapter 8 Management Register Set
8.13.8 Link Loss Inhibit (bit 18.1)
The Link Loss Inhibit bit allows an STA to prevent the ICS1893 from dropping the link in 10Base-T mode.
When an STA sets this bit to logic:
• Zero, the state machine behaves normally and the link status is based on the signaling detected Twisted-
Pair Receiver inputs.
• One, the ICS1893 10Base-T Link Integrity Test state machine is forced into the ‘Link Passed’state
regardless of the Twisted-Pair Receiver input conditions.
8.13.9 Squelch Inhibit (bit 18.0)
The Squelch Inhibit bit allows an STA to control the ICS1893 Squelch Detection in 10Base-T mode. When
an STA sets this bit to logic:
• Zero, before the ICS1893 can establish a valid link, the ICS1893 must receive valid 10Base-T data.
• One, before the ICS1893 can establish a valid link, the ICS1893 must receive both valid 10Base-T data
followed by an IDL.
ICS1893 Rev C 6/6/00
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
99
June, 2000