ICS1893 Datasheet, PDF (131/152 Pages) Integrated Circuit Systems – 3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

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Chapter 10 DC and AC Operating Conditions
10.5.5 10M MII: Synchronous Transmit Timing
Table 10-12 lists the significant time periods for the 10M MII synchronous transmit timing. The time periods
consist of timings of signals on the following pins:
• TXCLK
• TXD[3:0]
• TXEN
• TXER
Figure 10-6 shows the timing diagram for the time periods.
Table 10-12. 10M MII: Synchronous Transmit Timing
Time
Period
t1
t2
Parameter
TXD[3:0], TXEN, TXER Setup to TXCLK Rise
TXD[3:0], TXEN, TXER Hold after TXCLK Rise
Conditions
–
–
Min.
375
0
Typ.
–
–
Max. Units
–
ns
–
ns
Figure 10-6. 10M MII Synchronous Transmit Timing Diagram
TXCLK
TXD[3:0]
TXEN
TXER
t1
t2
ICS1893 Rev C 6/6/00
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
131
June, 2000