ICS1893 Datasheet, PDF (144/152 Pages) Integrated Circuit Systems – 3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

ICS1893 Data Sheet - Release
Chapter 10 DC and AC Operating Conditions
10.5.18 Reset: Hardware Reset and Power-Down
Table 10-25 lists the significant time periods for the hardware reset and power-down reset. The time
periods consist of timings of signals on the following pins:
• REF_IN
• RESETn
• TXCLK
Figure 10-19 shows the timing diagram for the time periods.
Table 10-25. Hardware Reset and Power-Down Timing
Time
Period
Parameter
t1 RESETn Active to Device Isolation and Initialization
t2 Minimum RESETn Pulse Width
t3 RESETn Released to TXCLK Valid
Condi-
tions
–
–
–
Min. Typ. Max. Units
– 60 –
ns
500 40 –
ns
– 35 500 ms
Figure 10-19. Hardware Reset and Power-Down Timing Diagram
REF_IN
RESETn
t1
t2
t3
TXCLK Valid
Power
Consumption
(AC only)
ICS1893 Rev C 6/6/00
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
144
June, 2000