ICS1893 Datasheet, PDF (19/152 Pages) Integrated Circuit Systems – 3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

ICS1893 - Release
Chapter 5 Operating Modes Overview
Chapter 5 Operating Modes Overview
The ICS1893 operating modes and interfaces are configurable with one of two methods. The HW/SW
(hardware/software) pin determines which method the ICS1893 is to use, either its hardware pins or its
register bits. When the HW/SW bit is logic zero the ICS1893 is in hardware mode. In hardware mode, the
hardware pins have priority over the internal registers for establishing the configuration settings of the
ICS1893. When the HW/SW bit is logic one the ICS1893 is in software mode. In software mode, the
internal register bits have priority over the hardware pins for establishing the configuration settings of the
ICS1893. The register bits are typically controlled from software.
The ICS1893 register bits are accessible through a standard MII (Media Independent Interface) Serial
Management Port. Even when the ICS1893 MAC/Repeater Interface is not supporting the standard MII
Data Interface, access to the Serial Management Port is provided (that is, operation of the Serial
Management Port is independent of the MAC/Repeater Interface configuration).
The ICS1893 provides a number of configuration functions to support a variety of operations. For example,
the MAC/Repeater Interface can be configured to operate as a 10M MII, a 100M MII, a 100M Symbol
Interface, a 10M Serial Interface, or a Link Pulse Interface. The protocol on the Medium Dependent
Interface (MDI) can be configured to support either 10M or 100M operations in either half-duplex or
full-duplex modes.
The ICS1893 is fully compliant with the ISO/IEC 8802-3 standard, as it pertains to both 10Base-T and
100Base-TX operations. The feature-rich ICS1893 allows easy migration from 10-Mbps to 100-Mbps
operations as well as from systems that require support of both 10M and 100M links.
This chapter is an overview of the following ICS1893 modes of operation:
• Section 5.1, “Reset Operations”
• Section 5.2, “Power-Down Operations”
• Section 5.3, “Automatic Power-Saving Operations”
• Section 5.4, “Auto-Negotiation Operations”
• Section 5.5, “100Base-TX Operations”
• Section 5.6, “10Base-T Operations”
• Section 5.7, “Half-Duplex and Full-Duplex Operations”
ICS1893 Rev C 6/6/00
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
19
June, 2000