ICS1893 Datasheet, PDF (135/152 Pages) Integrated Circuit Systems – 3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

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Chapter 10 DC and AC Operating Conditions
10.5.9 10M Media Independent Interface: Receive Latency
Table 10-16 lists the significant time periods for the 10M MII timing. The time periods consist of timings of
signals on the following pins:
• TP_RX (that is, the MII TP_RXP and TP_RXN pins)
• RXCLK
• RXD
Figure 10-10 shows the timing diagram for the time periods.
Table 10-16. 10M MII Receive Latency
Time
Period
Parameter
t1 First Bit of /5/ on TP_RX to /5/D/ on RXD
Conditions Min. Typ. Max. Units
10M MII
– 6.5 7 Bit times
Figure 10-10. 10M MII Receive Latency Timing Diagram
TP_RX^†
RXCLK
RXD
5
† _Manchester
encoding is
not shown.
5
t1
5
D
ICS1893 Rev C 6/6/00
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
135
June, 2000