ICS1893 Datasheet, PDF (111/152 Pages) Integrated Circuit Systems – 3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

ICS1893 - Release
Chapter 9 Pin Diagram, Listings, and Descriptions
Table 9-4. Configuration Pins (Continued)
Pin
Name
Pin
Pin
Number Type
Pin Description
HW/SW
LOCK
23
Input Hardware/Software (Select).
When the signal on this pin is logic:
• Low, this pin selects Hardware mode operations.
• High, this pin selects Software mode operations.
27
Output (Stream Cipher) Lock (Acquired).
When the signal on this pin is logic:
• Low, the ICS1893 does not have a lock on the data stream.
• High, the ICS1893 has a lock on the data stream.
LSTA
21
Output Link Status.
This pin is used to report the status of the link segment. When the
signal on this pin is logic:
• Low, there is no link established.
• High, there is a link established.
This pin is mapped according to the interface for which the ICS1893 is
mapped. For the:
• Media Independent Interface (MII), the LSTA is mapped as LSTA.
• 100M Symbol Interface, the LSTA is mapped as SD.
• 10M Serial Interface, the LSTA is mapped as LSTA.
• Link Pulse Interface, the LSTA is mapped as SD.
MII/SI
19
Input Media Independent Interface / Stream Interface (Select).
This pin is used in combination with the 10/LP and 10/100SEL pins to
configure the ICS1893 MAC/Repeater Interface. When the signal on
this pin is logic:
• Low, this pin configures the MAC/Repeater Interface as a Media
Independent Interface.
• High, this pin configures the MAC/Repeater Interface as a Stream
Interface.
NOD/REP
1
Input
Node/Repeater (Select).
This selection on this pin affects both the SQE test and the Carrier
Sense (CSR) signal. When the signal on this pin is logic:
• Low, this pin enables the ICS1893 to default to node operations.
• High, this pin enables the ICS1893 to default to repeater
operations.
REF_IN
53
REF_OUT
52
RESETn
18
Input
Input
Input
(Frequency) Reference Input.
This pin is connected to a 25-MHz oscillator. For a tolerance, see
Section 10.5.1, “Timing for Clock Reference In (REF_IN) Pin”.
(Frequency) Reference Output.
This pin is eserved and must be left unconnected.
(System) Reset (Active Low).
• When the signal on this active-low pin is logic:
– Low, the ICS1893 is in hardware reset.
– High, the ICS1893 is operational.
• For more information on hardware resets, see the following:
– Section 5.1.2.1, “Hardware Reset”
– Section 10.5.18, “Reset: Hardware Reset and Power-Down”
ICS1893 Rev C 6/6/00
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
111
June, 2000