ICS1893 Datasheet, PDF (65/152 Pages) Integrated Circuit Systems – 3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

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Chapter 8 Management Register Set
8.2.5 Low Power Mode (bit 0.11)
This bit provides one way to control the ICS1893 low-power mode function. When bit 0.11 is logic:
• Zero, there is no impact to ICS1893 operations.
• One, the ICS1893 enters the low-power mode. In this case, the ICS1893 disables all internal functions
and drives all MAC/repeater output pins low except for those that support the MII Serial Management
Port. In addition, the ICS1893 internally activates the TPTRI function to tri-state the signals on the
Twisted-Pair Transmit pins (TP_TXP and TP_TXN) and achieve additional power savings.
Note:
There are two ways the ICS1893 can enter low-power mode. When entering low-power mode:
• By setting bit 0.11 to logic one, the ICS1893 maintains the value of all Management Register bits
except the latching high (LH) and latching low (LL) status bits, which are re-initialized to their
default values instead. (For more information on latching high and latching low bits, see Section
8.1.4.1, “Latching High Bits”and Section 8.1.4.2, “Latching Low Bits”.)
• During a reset, the ICS1893 sets all management register bits to their default values.
8.2.6 Isolate (bit 0.10)
This bit controls the ICS1893 Isolate function. When bit 0.10 is logic:
• Zero, there is no impact to ICS1893 operations.
• One, the ICS1893 electrically isolates its data paths from the MAC/Repeater Interface. The ICS1893
places all MAC/repeater output signals (TXCLK, RXCLK, RXDV, RXER, RXD[3:0], COL, and CRS) in a
high-impedance state and it isolates all MAC/repeater input signals (TXD[3:0], TXEN, and TXER). In this
mode, the Serial Management Interface continues to operate normally (that is, bit 0.10 does not affect
the Management Interface).
The default value for bit 0.10 depends upon the PHY address of Table 8-16. If the PHY address:
• Is equal to 00000b, then the default value of bit 0.10 is logic one, and the ICS1893 isolates itself from the
MAC/Repeater Interface.
• Is not equal to 00000b, then the default value of bit 0.10 is logic zero, and the ICS1893 does not isolate
its MAC/Repeater Interface.
8.2.7 Restart Auto-Negotiation (bit 0.9)
This bit allows an STA to restart the auto-negotiation process in Software mode (that is, the HW/SW pin is
logic one). When bit 0.12 is logic:
• Zero, the Auto-Negotiation sublayer is disabled, and the ICS1893 isolates any attempt by the STA to set
bit 0.9 to logic one.
• One (as set by an STA), the ICS1893 restarts the auto-negotiation process. Once the auto-negotiation
process begins, the ICS1893 automatically sets this bit to logic zero, thereby providing the self-clearing
feature.
ICS1893 Rev C 6/6/00
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
65
June, 2000