ICS1893 Datasheet, PDF (91/152 Pages) Integrated Circuit Systems – 3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

ICS1893 - Release
Chapter 8 Management Register Set
8.12 Register 17: Quick Poll Detailed Status Register
Table 8-18 lists the bits for the Quick-Poll Detailed Status Register. This register is a 16-bit read-only
register used to provide an STA with detailed status of the ICS1893 operations. During reset, it is initialized
to pre-defined default values.
Note:
1. For an explanation of acronyms used in Table 8-18, see Chapter 1, “Abbreviations and Acronyms”.
2. Most of this register’s bits are latching high or latching low, which allows the ICS1893 to capture and
save the occurrence of an event for an STA to read. (For more information on latching high and
latching low bits, see Section 8.1.4.1, “Latching High Bits”and Section 8.1.4.2, “Latching Low Bits”.)
3. Although some of these status bits are redundant with other management registers, the ICS1893
provides this group of bits to minimize the number of Serial Management Cycles required to collect the
status data.
Table 8-18. Quick Poll Detailed Status Register (register 17 [0x11])
Bit
Definition
When Bit = 0
When Bit = 1
Ac-
cess
17.15 Data rate
10 Mbps
100 Mbps
RO
17.14 Duplex
Half duplex
Full duplex
RO
17.13 Auto-Negotiation
Reference Decode Table Reference Decode Table RO
Progress Monitor Bit 2
17.12 Auto-Negotiation
Reference Decode Table Reference Decode Table RO
Progress Monitor Bit 1
17.11 Auto-Negotiation
Reference Decode Table Reference Decode Table RO
Progress Monitor Bit 0
17.10 100Base-TX signal Valid signal
Signal lost
RO
lost
17.9 100BasePLL Lock
Error
PLL locked
PLL failed to lock
RO
17.8 False Carrier detect Normal Carrier or Idle False Carrier
RO
17.7 Invalid symbol
detected
Valid symbols observed Invalid symbol received RO
17.6 Halt Symbol detected No Halt Symbol received Halt Symbol received
RO
17.5 Premature End
detected
Normal data stream
Stream contained two
RO
IDLE symbols
17.4 Auto-Negotiation
Auto-Negotiation in
Auto-Negotiation
RO
complete
process
complete
17.3 100Base-TX signal No signal present
Signal present
RO
detect
17.2 Jabber detect
No jabber detected
Jabber detected
RO
17.1 Remote fault
No remote fault detected Remote fault detected
RO
17.0 Link Status
Link is not valid
Link is valid
RO
SF
–
–
LMX
LMX
LMX
LH
LH
LH
LH
LH
LH
–
–
LH
LH
LL
De- Hex
fault
––
–
0
0
00
0
0
0
00
0
0
0
00
0
0
0
ICS1893 Rev C 6/6/00
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
91
June, 2000