ICS1893 Datasheet, PDF (139/152 Pages) Integrated Circuit Systems – 3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

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Chapter 10 DC and AC Operating Conditions
10.5.13 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)
Table 10-20 lists the significant time periods for the 100M MII carrier assertion/de-assertion during
half-duplex transmission. The time periods consist of timings of signals on the following pins:
• TXEN
• TXCLK
• CRS
Figure 10-14 shows the timing diagram for the time periods.
Table 10-20. 100M MII Carrier Assertion/De-Assertion (Half-Duplex Transmission Only)
Time
Period
Parameter
t1 TXEN Sampled Asserted to CRS Assert
t2 TXEN De-Asserted to CRS De-Asserted
Condi- Min.
tions
0
0
Typ.
3
3
Max. Units
4 Bit times
4 Bit times
Figure 10-14. 100M MII Carrier Assertion/De-Assertion Timing Diagram
(Half-Duplex Transmission Only)
t2
TXEN
TXCLK
CRS
t1
ICS1893 Rev C 6/6/00
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
139
June, 2000