ICS1893 Datasheet, PDF (143/152 Pages) Integrated Circuit Systems – 3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

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Chapter 10 DC and AC Operating Conditions
10.5.17 Reset: Power-On Reset
Table 10-24 lists the significant time periods for the power-on reset. The time periods consist of timings of
signals on the following pins:
• VDD
• TXCLK
Figure 10-18 shows the timing diagram for the time periods.
Table 10-24. Power-On Reset Timing
Time
Period
Parameter
t1 VDD ≥ 2.7 V to Reset Complete
Conditions Min. Typ. Max. Units
–
40 45 500 ms
Figure 10-18. Power-On Reset Timing Diagram
VDD
2.7 V
t1
TXCLK
Valid
ICS1893 Rev C 6/6/00
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
143
June, 2000