ICS1893 Datasheet, PDF (76/152 Pages) Integrated Circuit Systems – 3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

ICS1893 Data Sheet - Release
Chapter 8 Management Register Set
8.6 Register 4: Auto-Negotiation Register
Table 8-11 lists the bits for the Auto-Negotiation Register. An STA uses this register to select the ICS1893
capabilities that it wants to advertise to its remote link partner. During the auto-negotiation process, the
ICS1893 advertises (that is, exchanges) capability data with its remote link partner by using a pre-defined
Link Code Word. The Link Code Word is embedded in the Fast Link Pulses exchanged between PHYs
when the ICS1893 has its Auto-Negotiation sublayer enabled. The value of the Link Control Word is
established based on the value of the bits in this register.
Note: For an explanation of acronyms used in Table 8-5, see Chapter 1, “Abbreviations and Acronyms”.
Table 8-11. Auto-Negotiation Advertisement Register (register 4 [0x04])
Bit
Definition
When Bit = 0
When Bit = 1
4.15 Next Page
Next page not supported Next page supported
4.14 IEEE reserved
Always 0
N/A
4.13 Remote fault
Locally, no faults detected Local fault detected
4.12 IEEE reserved
Always 0
N/A
4.11 IEEE reserved
Always 0
N/A
4.10 IEEE reserved
Always 0
N/A
4.9 100Base-T4
Always 0. (Not supported.) N/A
4.8 100Base-TX, full duplex Do not advertise ability
Advertise ability
4.7 100Base-TX, half duplex Do not advertise ability
Advertise ability
4.6 10Base-T, full duplex Do not advertise ability
Advertise ability
4.5 10Base-T half duplex Do not advertise ability
Advertise ability
4.4 Selector Field bit S4
IEEE 802.3-specified default N/A
4.3 Selector Field bit S3
IEEE 802.3-specified default N/A
4.2 Selector Field bit S2
IEEE 802.3-specified default N/A
4.1 Selector Field bit S1
IEEE 802.3-specified default N/A
4.0 Selector Field bit S0
N/A
IEEE 802.3-specified
default
Ac- SF De- Hex
cess
fault
R/W – 0 0
CW – 0†
R/W – 0
CW – 0†
CW – 0† 1
CW – 0†
CW – 0
Note 1 – 1
Note 1 – 1 E
Note 1 – 1
Note 1 – 1
CW – 0
CW – 0 1
CW – 0
CW – 0
CW – 1
† As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value
to all Reserved bits.
Note 1:
• In Hardware mode (that is, HW/SW pin is logic zero), this bit is a Read-Only bit.
• In Software mode (that is, HW/SW pin is logic one), this bit is a Command Override Write bit.
8.6.1 Next Page (bit 4.15)
This bit indicates whether the ICS1893 uses the Next Page Mode functions during the auto-negotiation
process. If bit 4.15 is logic:
• Zero, then the ICS1893 indicates to its remote link partner that these features are disabled. (Although
the default value of this bit is logic zero, the ICS1893 does support the Next Page function.)
• One, then the ICS1893 advertises to its remote link partner that this feature is enabled.
ICS1893 Rev C 6/6/00
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
76
June, 2000