ICS1893 Datasheet, PDF (113/152 Pages) Integrated Circuit Systems – 3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

ICS1893 - Release
Chapter 9 Pin Diagram, Listings, and Descriptions
Table 9-5. MAC/Repeater Interface Pins: Media Independent Interface (MII) (Continued)
Pin
Pin
Pin
Name Number Type
Pin Description
MDIO
30
Input/ Management Data Input/Output.
Output The signal on this pin can be tri-stated and can be driven by one of the
following:
• A Station Management Entity (STA), to transfer command and data
information to the registers of the ICS1893.
• The ICS1893, to transfer status information.
All transfers and sampling are synchronous with the signal on the MDC
pin.
Note: If the ICS1893 is to be used in an application that uses the
mechanical MII specification, MDIO must have a 1.5 kΩ ±5%
pull-up resistor at the ICS1893 end and a 2 kΩ ±5% pull-down
resistor at the station management end. (These resistors enable
the station management to determine if the connection is intact.)
RXCLK
38
Output Receive Clock.
The ICS1893 sources the RXCLK to the MAC/repeater interface. The
ICS1893 uses RXCLK to synchronize the signals on the following pins:
RXD[3:0], RXDV, and RXER. The following table contrasts the behavior
on the RXCLK pin when the mode for the ICS1893 is either 10Base-T or
100Base-TX.
10Base-T
100Base-TX
The RXCLK frequency is 2.5
MHz.
The RXCLK frequency is 25 MHz.
The ICS1893 generates its
RXCLK from the MDI data stream
using a digital PLL. When the MDI
data stream terminates, the PLL
continues to operate,
synchronously referenced to the
last packet received.
The ICS1893 generates its
RXCLK from the MDI data stream
while there is a valid link (that is,
either data or IDLEs). In the
absence of a link, the ICS1893
uses the REF_IN clock to
generate the RXCLK.
The ICS1893 switches between
clock sources during the period
between when its CRS is
asserted and prior to its RXDV
being asserted. While the
ICS1893 is locking onto the
incoming data stream, a clock
phase change of up to 360
degrees can occur.
While the ICS1893 is bringing up
a link, a clock phase change of up
to 360 degrees can occur.
The RXCLK aligns once per
packet.
The RXCLK aligns once, when
the link is being established.
Note: The signal on the RXCLK pin is conditioned by the RXTRI pin.
ICS1893 Rev C 6/6/00
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
113
June, 2000