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ICS1893 Datasheet, PDF (59/152 Pages) Integrated Circuit Systems – 3.3-V 10Base-T/100Base-TX Integrated PHYceiver™ | |||
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ICS1893 - Release
Chapter 8 Management Register Set
Chapter 8 Management Register Set
The tables in this chapter detail the functionality of the bits in the management register set. The tables
include the register locations, the bit positions, the bit definitions, the STA Read/Write Access Types, the
default bit values, and any special bit functions or capabilities (such as self-clearing). Following each table
is a description of each bit. This chapter includes the following sections:
⢠Section 8.1, âIntroduction to Management Register Setâ
⢠Section 8.2, âRegister 0: Control Registerâ
⢠Section 8.3, âRegister 1: Status Registerâ
⢠Section 8.4, âRegister 2: PHY Identifier Registerâ
⢠Section 8.5, âRegister 3: PHY Identifier Registerâ
⢠Section 8.6, âRegister 4: Auto-Negotiation Registerâ
⢠Section 8.7, âRegister 5: Auto-Negotiation Link Partner Ability Registerâ
⢠Section 8.8, âRegister 6: Auto-Negotiation Expansion Registerâ
⢠Section 8.9, âRegister 7: Auto-Negotiation Next Page Transmit Registerâ
⢠Section 8.10, âRegister 8: Auto-Negotiation Next Page Link Partner Ability Registerâ
⢠Section 8.11, âRegister 16: Extended Control Registerâ
⢠Section 8.12, âRegister 17: Quick Poll Detailed Status Registerâ
⢠Section 8.13, âRegister 18: 10Base-T Operations Registerâ
⢠Section 8.14, âRegister 19: Extended Control Register 2â
ICS1893 Rev C 6/6/00
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
59
June, 2000
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