ICS1893 Datasheet, PDF (61/152 Pages) Integrated Circuit Systems – 3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

ICS1893 - Release
Chapter 8 Management Register Set
8.1.2 Management Register Bit Access
The ICS1893 Management Registers include one or more of the following types of bits:
Table 8-3. Description of Management Register Bit Types
Management
Register Bit Types
Read-Only
Command Override
Write
Read/Write
Read/Write Zero
Bit
Symbol
Description
RO An STA can obtain the value of a RO register bit. However, it cannot
alter the value of (that is, it cannot write to) an RO register bit. The
ICS1893 isolates any STA attempt to write a value to an RO bit.
CW An STA can read a value from a CW register bit. However, write
operations are conditional, based on the value of the Command
Register Override bit (bit 16.15). When bit 16.15 is logic:
• Zero (the default), the ICS1893 isolates STA attempts to write to
the CW bits (that is, CW bits cannot be altered when bit 16.15 is
logic zero).
• One, the ICS1893 permits an STA to alter the value of the CW bits
in the subsequent register write. (Bit 16.15 is self-clearing and
automatically clears to zero on the subsequent write.)
R/W An STA can unconditionally read from or write to a R/W register bit.
R/W0 An STA can unconditionally read from a R/W0 register bit, but only a
‘0’value can be written to this bit.
8.1.3 Management Register Bit Default Values
The tables in this chapter specify for each register bit the default value, if one exists. The ICS1893 sets all
Management Register bits to their default values after a reset. Table 8-4 lists the valid default values for
ICS1893 Management Register bits.
Table 8-4. Range of Possible Valid Default Values for ICS1893 Register Bits
Default Condition
–
0
1
State of pin at reset
Default Value
Indicates there is no default value for the bit
Indicates the bit’s default value is logic zero
Indicates the bit’s default value is logic one
For some bits, the default value depends on the state (that is, the logic value) of a
particular pin at reset (that is, the logic value of a pin is latched at reset). An
example of pins that have a default condition that depends on the state of the pin
at reset are the PHY / LED pins (P0AC, P1CL, P2LI, P3TD, and P4RD) discussed
in the following sections:
• Section 6.8, “Status Interface”
• Section 8.11, “Register 16: Extended Control Register”
• Section 9.3.2, “Multi-Function (Multiplexed) Pins: PHY Address and LED Pins”
Note:
The ICS1893 has a number of reserved bits throughout the Management Registers. Most of these
bits provide enhanced test modes. The Management Register tables provide the default values for
these bits. The STA must not change the value of these bits under any circumstance. If the STA
inadvertently changes the default values of these reserved register bits, normal operation of the
ICS1893 can be affected.
ICS1893 Rev C 6/6/00
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
61
June, 2000