ICS1893 Datasheet, PDF (138/152 Pages) Integrated Circuit Systems – 3.3-V 10Base-T/100Base-TX Integrated PHYceiver™

ICS1893 Data Sheet - Release
Chapter 10 DC and AC Operating Conditions
10.5.12 MII / 100M Stream Interface: Transmit Latency
Table 10-19 lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time
periods consist of timings of signals on the following pins:
• TXEN
• TXCLK
• TXD (that is, TXD[3:0])
• TP_TX (that is, TP_TXP and TP_TXN)
Figure 10-13 shows the timing diagram for the time periods.
Table 10-19. MII / 100M Stream Interface Transmit Latency
Time
Period
Parameter
Conditions
Min. Typ. Max. Units
t1 TXEN Sampled to MDI Output of First MII mode
Bit of /J/ †
– 2.8 3 Bit times
t2 TXD Sampled to MDI Output of First 100M Stream Interface – 6.1 7 Bit times
Bit of /J/ †
† The IEEE maximum is 18 bit times.
Figure 10-13. MII / 100M Stream Interface Transmit Latency Timing Diagram
TXEN
TXCLK
TXD
Preamble /J/ Preamble /K/
TP_TX^†
t1
t2
† _Shown
unscrambled.
ICS1893 Rev C 6/6/00
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
138
June, 2000