H27U4G8F2D Datasheet, PDF (59/62 Pages) Hynix Semiconductor – 4 Gbit (512M x 8 bit) NAND Flash

APCPCWM_4828539:WP_0000001WP_0000001
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H27(U_S)4G8_6F2D
4 Gbit (512M x 8 bit) NAND Flash
x8
x8
R
1
R
2
R
3
R/B4#
4
R/B3#
5
R/B2#
6
R/B1#
7
RE#
8
CE1#
9
CE2#
10
R
11
Vcc
12
Vss
13
CE3#
14
CE4#
15
CLE
16
ALE
17
WE#
18
WP#
19
R
R
R
R
R
20
21
22
23
24
48
47
46
45
44
R/Vss
R
R
R
IO7
43
IO6
42
IO5
41
IO4
40
R
39
R/Vcc
38
R
37
Vcc
36
Vss
35
R
34
R/Vcc
33
R
32
IO3
31
IO2
30
IO1
29
IO0
28
R
27
R
26
R
25
R/Vss
Figure 44: ONFI 1.0 TSOP and WSOP connection (x8 multi CE# / multi RyBYconfiguration) (*)
NOTES:
1) TSOP48 "ONFI" is supported only for x8 I/O configuration
2) Pins marked in Red are used in case a quad stack die is implemented with separated RyBy and CE# pins. If this is not
the case, CE# for the stack is pin 9, and RyBy# for the stack is pin 7, and pins marked in Red Bold are Reserved ("R")
3) this package is supported only if die is mounted OVER package frame
7.1 Power consumptions and pin capacitance for allowed stacking configurations
Table 28 reports the power consumptions related to the single chip case. When multiple dice are stacked in the same
package the power consumption of the stack will increase according to the nr of chips of it. As an example, the standby
current is the sum of the standby currents of all the chips, while the active power consumption depends on the nr of chips
concurrently executing different operations.
Similarly, Table 26 reports the pin capacitance for the single chip case. When multiple dice are stacked in the same pack-
age the pin/ball capacitance for the single input and the single input/output of the combo package must be calculated
based on the number of chips sharing that input or that pin/ball.
Rev 1.4 / OCT. 2010
*ba53f20d-240c*
59
B34416/177.179.157.84/2010-10-08 10:08