H27U4G8F2D Datasheet, PDF (42/62 Pages) Hynix Semiconductor – 4 Gbit (512M x 8 bit) NAND Flash

APCPCWM_4828539:WP_0000001WP_0000001
Block Erase Operation
1
H27(U_S)4G8_6F2D
4 Gbit (512M x 8 bit) NAND Flash
CLE
CE
WE
ALE
RE
IOx
R/B
tWC
tWB
60h Row Add1 Row Add2 Row Add3 D0h
Row Address
Auto Block Erase
Setup Command
Erase Command
tBERS
BUSY
tWHR
70h
I/O0
Read Status ^{IO0=0 Successful Erase}
Command IO0=1 Error in Erase
Figure 19: Block Erase Operation (Erase One Block)
Two-Plane Page Program Operation
CLE
CE
tWC
WE
ALE
tWB ^tDBSY
tWB tPROG
RE
tADL
tADL
I/Ox
80h
Serial Data
Input Command
Col.
Add1
Col.
Add2
Row
Add1
Row
Add2
Row
Add3
Column Address Page Row Address
Din
Din
N
M
1 up to 2112 Byte
Data Serial Input
11h
Program
Command
(Dummy)
81h
R/B
Ex.) Tow-Plane Page Program
tDBSY: typ. 500us
max. 1us
R/B
tDBSY
Col.
Add1
Col.
Add2
Row
Add1
Row
Add2
Row
Add3
Din
N
Din
M
10h
Program Confirm
Command (True)
tPROG
IO 0~7 _80h
Address & Data Input
11h
81h
Address & Data Input
10h
70h
Col Add 1,2 & Row Add 1,2,3
2112 Byte Data)
Note
Col Add 1,2 & Row Add 1,2,3
2112 Byte Data)
A0 ~ A11 : Valid
A12 ~ A17 : Fixed ‘Low’
A18
: Fixed ‘Low’
A19 ~ A28 : Fixed ‘Low’
A0 ~ A11 : Valid
A12 ~ A17 : Valid
A18
: Fixed “High’
A19 ~ A28 : Valid
Note : Any command between 11h and 81h is prohibited except 70h and FFh
NOTES:
1) the figure refers to x8 case. Please refer to Section 1.4 for address remapping rules for the x16 case
2) any command between 11h and 81h is prohibited except 70h, 78h and FFh
Figure 20: Multiple plane page program (traditional protocol)
tWHR
70h
IO
Read Staus
Command
Rev 1.4 / OCT. 2010
42
*ba53f20d-240c*
B34416/177.179.157.84/2010-10-08 10:08