H27U4G8F2D Datasheet, PDF (20/62 Pages) Hynix Semiconductor – 4 Gbit (512M x 8 bit) NAND Flash

APCPCWM_4828539:WP_0000001WP_0000001
1
H27(U_S)4G8_6F2D
4 Gbit (512M x 8 bit) NAND Flash
3.13 Read Status Register field definition
Table 12 below lists the meaning of each bit of Read Status Register and Read Status Enhanced
Page
IO
Program/
Page
Reprogram
0
Pass / Fail
Block
Erase
Pass / Fail
Read
NA
Cache
Read
NA
Cache
Program/
Cache
reprogram
Pass / Fail
1
NA
NA
NA
NA
Pass / Fail
2
NA
NA
NA
NA
NA
3
NA
NA
NA
NA
NA
4
NA
NA
NA
NA
NA
5 Ready / Busy Ready / Busy Ready / Busy Ready / Busy Ready / Busy
6 Ready / Busy Ready / Busy Ready / Busy Ready / Busy Ready / Busy
7
Write
Protect
Write
Protect
Write
Protect
Write
Protect
Write
Protect
CODING
N Page
Pass: ‘0’ Fail: ‘1’
N - Page
Pass: ‘0’ Fail: ‘1’
-
-
-
Active: ‘0’
Idle: ‘1’
Data cache Read/Busy
Busy: ‘0’ Ready: ‘1’
Protected: ‘0’
Not Protected: ‘1’
Table 12: Status Register Coding
3.14 Read EDC status register
This operation is available only in copy back program and it allows the detection of errors occurred during read for copy
back. In case of multiple plane copy back, it is not possible to know which of the two read operation caused the error.
After writing Read EDC status register command (7Bh) to the command register, a read cycle outputs the content of the
EDC Register to the I/O pins on the falling edge of CE# or RE#, whichever occurs last.
Operation is same as read status register command. Refer to Table 13 for specific EDC Register definitions:
IO
Copy back
program
0 Pass / Fail
1 EDC status
2 EDC validity
3 NA
4 NA
5 Ready / Busy
6 Ready / Busy
7 Write Protect
CODING
Pass: ‘0’ Fail: ‘1’
No error: ‘0’ Error: ‘1’
Invalid: ‘0’ Valid: ‘1’
-
-
Busy: ‘0’ Ready: ‘1’
Busy: ‘0’ Ready: ‘1’
Protected: ‘0’ Not Protected: ‘1’
Table 13: EDC register coding
Rev 1.4 / OCT. 2010
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*ba53f20d-240c*
B34416/177.179.157.84/2010-10-08 10:08