H27U4G8F2D Datasheet, PDF (57/62 Pages) Hynix Semiconductor – 4 Gbit (512M x 8 bit) NAND Flash

APCPCWM_4828539:WP_0000001WP_0000001
1
H27(U_S)4G8_6F2D
4 Gbit (512M x 8 bit) NAND Flash
Command Input
80h Address Input
RY/BY
A13~A17:Fixed”Low”
A18:Fixed”Low”
A19~A31:Fixed”Low”
Data Input
Return to 1
Repeat a max of 63 times
Command Input
80h Address Input
RY/BY
A13~A17:Fixed”Low”
A18:Fixed”Low”
A19~A31:Fixed”Low”
1
Data Input
11h
80h
t_DBSY
Address Input
A13~A17:Valid
A18:Fixed”Low”
A19~A31:Fixed”Low”
Data Input
11h
80h
t_DBSY
Address Input
A13~A17:Valid
A18:Fixed”Low”
A19~A31:Fixed”Low”
Data Input
15h
t_PCBSY
1
10h
t_PROG
CLE
CE
tWB
WE
ALE
tWC
tWB
RE
IOx
R/B
tADL
80h
Col. Col. Row Row Row
Din
Add1 Add2 Add1 Add2 Add3
N
Column Address Row Address
CLE
CE
WE
ALE
RE
IOx
R/B
1
tWB
80h
Col. Col. Row Row Row
Din
Add1 Add2 Add1 Add2 Add3
N
Column Address Row Address
Din
M
11h
tADL
80h
Col. Col. Row Row Row
Din
Add1 Add2 Add1 Add2 Add3
N
Column Address Row Address
tDBSY
tWC
Din
M
11h
80h
Col. Col. Row Row Row
Din
Add1 Add2 Add1 Add2 Add3
N
Column Address Row Address
tDBSY
Din
M
15h
tCBSY
1
Din
M
10h
F1h I/OQ
tPROG
Figure 42: multi-plane cache program (ONFI protocol)
NOTE:
3) the figure refers to x8 case. Please refer to Section 1.4 for address remapping rules for the x16 case
4) Read Status register (70h) is used in the figure. Read Status Enhanced (78h) can be also used
Rev 1.4 / OCT. 2010
57
*ba53f20d-240c*
B34416/177.179.157.84/2010-10-08 10:08